Lines Matching refs:BIT
89 #define SATA_RST_N BIT(0) /* Active low reset sata_core phy */
90 #define SataCtlReserve0 BIT(1)
91 #define M_CSYSREQ BIT(2) /* AXI master low power, not used */
92 #define S_CSYSREQ BIT(3) /* AXI slave low power, not used */
93 #define P0_CP_DET BIT(8) /* Reserved, bring in from pad */
94 #define P0_MP_SW BIT(9) /* Mech Switch */
95 #define P0_DISABLE BIT(10) /* disable p0 */
96 #define P0_ACT_LED_EN BIT(11) /* Active LED enable */
97 #define P0_IRST_HARD_SYNTH BIT(12) /* PHY hard synth reset */
98 #define P0_IRST_HARD_TXRX BIT(13) /* PHY lane hard reset */
99 #define P0_IRST_POR BIT(14) /* PHY power on reset*/
100 #define P0_IPDTXL BIT(15) /* PHY Tx lane dis/power down */
101 #define P0_IPDRXL BIT(16) /* PHY Rx lane dis/power down */
102 #define P0_IPDIPDMSYNTH BIT(17) /* PHY synthesizer dis/porwer down */
103 #define P0_CP_POD_EN BIT(18) /* CP_POD enable */
104 #define P0_AT_BYPASS BIT(19) /* P0 address translation by pass */
105 #define P1_CP_DET BIT(20) /* Reserved,Cold Detect */
106 #define P1_MP_SW BIT(21) /* Mech Switch */
107 #define P1_DISABLE BIT(22) /* disable p1 */
108 #define P1_ACT_LED_EN BIT(23) /* Active LED enable */
109 #define P1_IRST_HARD_SYNTH BIT(24) /* PHY hard synth reset */
110 #define P1_IRST_HARD_TXRX BIT(25) /* PHY lane hard reset */
111 #define P1_IRST_POR BIT(26) /* PHY power on reset*/
112 #define P1_IPDTXL BIT(27) /* PHY Tx lane dis/porwer down */
113 #define P1_IPDRXL BIT(28) /* PHY Rx lane dis/porwer down */
114 #define P1_IPDIPDMSYNTH BIT(29) /* PHY synthesizer dis/porwer down */
115 #define P1_CP_POD_EN BIT(30)
116 #define P1_AT_BYPASS BIT(31) /* P1 address translation by pass */
119 #define M_CACTIVE BIT(0) /* m_cactive, not used */
120 #define S_CACTIVE BIT(1) /* s_cactive, not used */
121 #define P0_PHY_READY BIT(8) /* phy is ready */
122 #define P0_CP_POD BIT(9) /* Cold PowerOn */
123 #define P0_SLUMBER BIT(10) /* power mode slumber */
124 #define P0_PATIAL BIT(11) /* power mode patial */
125 #define P0_PHY_SIG_DET BIT(12) /* phy dignal detect */
126 #define P0_PHY_CALI BIT(13) /* phy calibration done */
127 #define P1_PHY_READY BIT(16) /* phy is ready */
128 #define P1_CP_POD BIT(17) /* Cold PowerOn */
129 #define P1_SLUMBER BIT(18) /* power mode slumber */
130 #define P1_PATIAL BIT(19) /* power mode patial */
131 #define P1_PHY_SIG_DET BIT(20) /* phy dignal detect */
132 #define P1_PHY_CALI BIT(21) /* phy calibration done */