Lines Matching refs:ir
852 mips_instruction ir) in cop1_cfc() argument
857 switch (MIPSInst_RD(ir)) { in cop1_cfc()
861 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
871 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
879 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
890 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
901 if (MIPSInst_RT(ir)) in cop1_cfc()
902 xcp->regs[MIPSInst_RT(ir)] = value; in cop1_cfc()
909 mips_instruction ir) in cop1_ctc() argument
915 if (MIPSInst_RT(ir) == 0) in cop1_ctc()
918 value = xcp->regs[MIPSInst_RT(ir)]; in cop1_ctc()
920 switch (MIPSInst_RD(ir)) { in cop1_ctc()
923 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
934 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
945 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
954 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
979 mips_instruction ir; in cop1Emulate() local
1018 ir = dec_insn.next_insn; /* process delay slot instr */ in cop1Emulate()
1021 ir = dec_insn.insn; /* process current instr */ in cop1Emulate()
1042 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) in cop1Emulate()
1050 switch (MIPSInst_OPCODE(ir)) { in cop1Emulate()
1052 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1053 MIPSInst_SIMM(ir)); in cop1Emulate()
1066 DITOREG(dval, MIPSInst_RT(ir)); in cop1Emulate()
1070 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1071 MIPSInst_SIMM(ir)); in cop1Emulate()
1073 DIFROMREG(dval, MIPSInst_RT(ir)); in cop1Emulate()
1087 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1088 MIPSInst_SIMM(ir)); in cop1Emulate()
1100 SITOREG(wval, MIPSInst_RT(ir)); in cop1Emulate()
1104 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1105 MIPSInst_SIMM(ir)); in cop1Emulate()
1107 SIFROMREG(wval, MIPSInst_RT(ir)); in cop1Emulate()
1121 switch (MIPSInst_RS(ir)) { in cop1Emulate()
1127 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
1128 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1129 MIPSInst_RD(ir)); in cop1Emulate()
1138 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1146 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
1147 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1148 MIPSInst_RD(ir)); in cop1Emulate()
1157 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1162 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
1163 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1164 MIPSInst_RD(ir)); in cop1Emulate()
1170 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1175 cop1_cfc(xcp, ctx, ir); in cop1Emulate()
1180 cop1_ctc(xcp, ctx, ir); in cop1Emulate()
1192 switch (MIPSInst_RS(ir)) { in cop1Emulate()
1194 if (get_fpr32(¤t->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1) in cop1Emulate()
1198 if (!(get_fpr32(¤t->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1)) in cop1Emulate()
1209 cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; in cop1Emulate()
1215 switch (MIPSInst_RT(ir) & 3) { in cop1Emulate()
1246 contpc = MIPSInst_SIMM(ir); in cop1Emulate()
1247 ir = dec_insn.next_insn; in cop1Emulate()
1253 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { in cop1Emulate()
1263 ir = (ir & (~0xffff)) | MM_NOP16; in cop1Emulate()
1269 sig = mips_dsemul(xcp, ir, in cop1Emulate()
1282 switch (MIPSInst_OPCODE(ir)) { in cop1Emulate()
1305 switch (MIPSInst_FUNC(ir)) { in cop1Emulate()
1323 sig = mips_dsemul(xcp, ir, contpc); in cop1Emulate()
1343 if (!(MIPSInst_RS(ir) & 0x10)) in cop1Emulate()
1347 if ((sig = fpu_emu(xcp, ctx, ir))) in cop1Emulate()
1356 sig = fpux_emu(xcp, ctx, ir, fault_addr); in cop1Emulate()
1365 if (MIPSInst_FUNC(ir) != movc_op) in cop1Emulate()
1367 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; in cop1Emulate()
1368 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) in cop1Emulate()
1369 xcp->regs[MIPSInst_RD(ir)] = in cop1Emulate()
1370 xcp->regs[MIPSInst_RS(ir)]; in cop1Emulate()
1458 mips_instruction ir, void *__user *fault_addr) in fpux_emu() argument
1464 switch (MIPSInst_FMA_FFMT(ir)) { in fpux_emu()
1472 switch (MIPSInst_FUNC(ir)) { in fpux_emu()
1474 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1475 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1488 SITOREG(val, MIPSInst_FD(ir)); in fpux_emu()
1492 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1493 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1497 SIFROMREG(val, MIPSInst_FS(ir)); in fpux_emu()
1524 SPFROMREG(fr, MIPSInst_FR(ir)); in fpux_emu()
1525 SPFROMREG(fs, MIPSInst_FS(ir)); in fpux_emu()
1526 SPFROMREG(ft, MIPSInst_FT(ir)); in fpux_emu()
1528 SPTOREG(fd, MIPSInst_FD(ir)); in fpux_emu()
1569 switch (MIPSInst_FUNC(ir)) { in fpux_emu()
1571 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1572 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1585 DITOREG(val, MIPSInst_FD(ir)); in fpux_emu()
1589 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1590 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1593 DIFROMREG(val, MIPSInst_FS(ir)); in fpux_emu()
1620 DPFROMREG(fr, MIPSInst_FR(ir)); in fpux_emu()
1621 DPFROMREG(fs, MIPSInst_FS(ir)); in fpux_emu()
1622 DPFROMREG(ft, MIPSInst_FT(ir)); in fpux_emu()
1624 DPTOREG(fd, MIPSInst_FD(ir)); in fpux_emu()
1634 if (MIPSInst_FUNC(ir) != pfetch_op) in fpux_emu()
1653 mips_instruction ir) in fpu_emu() argument
1669 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { in fpu_emu()
1677 switch (MIPSInst_FUNC(ir)) { in fpu_emu()
1723 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; in fpu_emu()
1725 ((MIPSInst_FT(ir) & 1) != 0)) in fpu_emu()
1727 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1734 if (xcp->regs[MIPSInst_FT(ir)] != 0) in fpu_emu()
1736 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1743 if (xcp->regs[MIPSInst_FT(ir)] == 0) in fpu_emu()
1745 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1752 SPFROMREG(rv.s, MIPSInst_FT(ir)); in fpu_emu()
1756 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1763 SPFROMREG(rv.s, MIPSInst_FT(ir)); in fpu_emu()
1765 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1776 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1777 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1778 SPFROMREG(fd, MIPSInst_FD(ir)); in fpu_emu()
1789 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1790 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1791 SPFROMREG(fd, MIPSInst_FD(ir)); in fpu_emu()
1802 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1814 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1826 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1827 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1838 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1839 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1850 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1851 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1862 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1863 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1878 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1883 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1884 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1889 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1920 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1926 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1939 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1940 ieee754_csr.rm = MIPSInst_FUNC(ir); in fpu_emu()
1950 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1963 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1964 ieee754_csr.rm = MIPSInst_FUNC(ir); in fpu_emu()
1971 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) { in fpu_emu()
1972 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; in fpu_emu()
1975 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1976 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2000 switch (MIPSInst_FUNC(ir)) { in fpu_emu()
2043 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; in fpu_emu()
2045 ((MIPSInst_FT(ir) & 1) != 0)) in fpu_emu()
2047 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2053 if (xcp->regs[MIPSInst_FT(ir)] != 0) in fpu_emu()
2055 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2061 if (xcp->regs[MIPSInst_FT(ir)] == 0) in fpu_emu()
2063 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2070 DPFROMREG(rv.d, MIPSInst_FT(ir)); in fpu_emu()
2074 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2081 DPFROMREG(rv.d, MIPSInst_FT(ir)); in fpu_emu()
2083 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2094 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2095 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2096 DPFROMREG(fd, MIPSInst_FD(ir)); in fpu_emu()
2107 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2108 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2109 DPFROMREG(fd, MIPSInst_FD(ir)); in fpu_emu()
2120 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2132 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2144 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2145 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2156 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2157 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2168 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2169 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2180 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2181 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2196 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2201 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2202 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2207 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2215 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2224 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2237 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2238 ieee754_csr.rm = MIPSInst_FUNC(ir); in fpu_emu()
2248 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2261 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2262 ieee754_csr.rm = MIPSInst_FUNC(ir); in fpu_emu()
2269 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) { in fpu_emu()
2270 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; in fpu_emu()
2273 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2274 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2298 switch (MIPSInst_FUNC(ir)) { in fpu_emu()
2301 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2307 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2317 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK; in fpu_emu()
2318 int sig = MIPSInst_FUNC(ir) & SIGN_BIT; in fpu_emu()
2323 (MIPSInst_FUNC(ir) & 0x20)) in fpu_emu()
2332 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2333 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2336 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { in fpu_emu()
2377 DIFROMREG(bits, MIPSInst_FS(ir)); in fpu_emu()
2379 switch (MIPSInst_FUNC(ir)) { in fpu_emu()
2392 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK; in fpu_emu()
2393 int sig = MIPSInst_FUNC(ir) & SIGN_BIT; in fpu_emu()
2397 (MIPSInst_FUNC(ir) & 0x20)) in fpu_emu()
2406 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2407 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2410 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { in fpu_emu()
2468 cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; in fpu_emu()
2478 DPTOREG(rv.d, MIPSInst_FD(ir)); in fpu_emu()
2481 SPTOREG(rv.s, MIPSInst_FD(ir)); in fpu_emu()
2484 SITOREG(rv.w, MIPSInst_FD(ir)); in fpu_emu()
2490 DITOREG(rv.l, MIPSInst_FD(ir)); in fpu_emu()