Lines Matching refs:MIPSInst_RT
861 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
871 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
879 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
890 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
901 if (MIPSInst_RT(ir)) in cop1_cfc()
902 xcp->regs[MIPSInst_RT(ir)] = value; in cop1_cfc()
915 if (MIPSInst_RT(ir) == 0) in cop1_ctc()
918 value = xcp->regs[MIPSInst_RT(ir)]; in cop1_ctc()
923 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
934 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
945 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
954 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
1066 DITOREG(dval, MIPSInst_RT(ir)); in cop1Emulate()
1073 DIFROMREG(dval, MIPSInst_RT(ir)); in cop1Emulate()
1100 SITOREG(wval, MIPSInst_RT(ir)); in cop1Emulate()
1107 SIFROMREG(wval, MIPSInst_RT(ir)); in cop1Emulate()
1127 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
1128 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1138 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1146 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
1147 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1157 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1162 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
1163 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1170 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1194 if (get_fpr32(¤t->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1) in cop1Emulate()
1198 if (!(get_fpr32(¤t->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1)) in cop1Emulate()
1209 cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; in cop1Emulate()
1215 switch (MIPSInst_RT(ir) & 3) { in cop1Emulate()
1367 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; in cop1Emulate()
1368 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) in cop1Emulate()