58 #define ADDC(sum,reg)						\  argument
61 	ADD	sum, reg;					\
62 	sltu	v1, sum, reg;					\
63 	ADD	sum, v1;					\
66 #define ADDC32(sum,reg)						\  argument
69 	addu	sum, reg;					\
70 	sltu	v1, sum, reg;					\
71 	addu	sum, v1;					\
74 #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)	\  argument
81 	ADDC(sum, _t0);						\
82 	ADDC(sum, _t2)
85 #define CSUM_BIGCHUNK(src, offset, sum, _t0, _t1, _t2, _t3)	\  argument
86 	CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)
88 #define CSUM_BIGCHUNK(src, offset, sum, _t0, _t1, _t2, _t3)	\  argument
89 	CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3);	\
90 	CSUM_BIGCHUNK1(src, offset + 0x10, sum, _t0, _t1, _t2, _t3)
100 #define sum v0  macro
106 	move	sum, zero
124 	ADDC(sum, t0)
134 	ADDC(sum, t0)
148 	ADDC(sum, t0)
159 	ADDC(sum, t0)
164 	ADDC(sum, t0)
165 	ADDC(sum, t1)
177 	ADDC(sum, t0)
178 	ADDC(sum, t1)
180 	CSUM_BIGCHUNK1(src, 0x00, sum, t0, t1, t3, t4)
191 	CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
192 	CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
193 	CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4)
194 	CSUM_BIGCHUNK(src, 0x60, sum, t0, t1, t3, t4)
206 	CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
207 	CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
215 	CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
227 	ADDC(sum, t0)
247 	ADDC(sum, t1)
268 1:	ADDC(sum, t1)
272 	dsll32	v1, sum, 0
273 	daddu	sum, v1
274 	sltu	v1, sum, v1
275 	dsra32	sum, sum, 0
276 	addu	sum, v1
283 	wsbh	v1, sum
284 	movn	sum, v1, t7
290 	and	t0, sum, v1
292 	srl	sum, sum, 8
293 	and	sum, sum, v1
294 	or	sum, sum, t0
299 	ADDC32(sum, a2)
319 #define sum v0  macro
464 	move	sum, zero
509 	ADDC(sum, t0)
513 	ADDC(sum, t2)
517 	ADDC(sum, t4)
521 	ADDC(sum, t6)
549 	ADDC(sum, t0)
553 	ADDC(sum, t2)
569 	ADDC(sum, t0)
597 	ADDC(sum, t0)
620 	ADDC(sum, t3)
654 	ADDC(sum, t0)
658 	ADDC(sum, t2)
675 	ADDC(sum, t0)
719 	ADDC(sum, t2)
725 	dsll32	v1, sum, 0
726 	daddu	sum, v1
727 	sltu	v1, sum, v1
728 	dsra32	sum, sum, 0
729 	addu	sum, v1
735 	wsbh	v1, sum
736 	movn	sum, v1, odd
742 	and	t0, sum, v1
744 	srl	sum, sum, 8
745 	and	sum, sum, v1
746 	or	sum, sum, t0
751 	ADDC32(sum, psum)
775 	ADDC(sum, t1)