510 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)  in simulate_ll()  argument
521 	offset = opcode & OFFSET;  in simulate_ll()
526 		((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);  in simulate_ll()
544 	regs->regs[(opcode & RT) >> 16] = value;  in simulate_ll()
549 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)  in simulate_sc()  argument
561 	offset = opcode & OFFSET;  in simulate_sc()
566 		((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);  in simulate_sc()
567 	reg = (opcode & RT) >> 16;  in simulate_sc()
597 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)  in simulate_llsc()  argument
599 	if ((opcode & OPCODE) == LL) {  in simulate_llsc()
602 		return simulate_ll(regs, opcode);  in simulate_llsc()
604 	if ((opcode & OPCODE) == SC) {  in simulate_llsc()
607 		return simulate_sc(regs, opcode);  in simulate_llsc()
652 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)  in simulate_rdhwr_normal()  argument
654 	if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {  in simulate_rdhwr_normal()
655 		int rd = (opcode & RD) >> 11;  in simulate_rdhwr_normal()
656 		int rt = (opcode & RT) >> 16;  in simulate_rdhwr_normal()
666 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode)  in simulate_rdhwr_mm()  argument
668 	if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {  in simulate_rdhwr_mm()
669 		int rd = (opcode & MM_RS) >> 16;  in simulate_rdhwr_mm()
670 		int rt = (opcode & MM_RT) >> 21;  in simulate_rdhwr_mm()
679 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)  in simulate_sync()  argument
681 	if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {  in simulate_sync()
763 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,  in simulate_fp()  argument
766 	union mips_instruction inst = { .word = opcode };  in simulate_fp()
772 	switch (inst.i_format.opcode) {  in simulate_fp()
938 	unsigned int opcode, bcode;  in do_bp()  local
964 			opcode = (instr[0] << 16) | instr[1];  in do_bp()
965 			bcode = (opcode >> 6) & ((1 << 20) - 1);  in do_bp()
968 		if (__get_user(opcode, (unsigned int __user *)epc))  in do_bp()
970 		bcode = (opcode >> 6) & ((1 << 20) - 1);  in do_bp()
1029 	u32 opcode, tcode = 0;  in do_tr()  local
1045 		opcode = (instr[0] << 16) | instr[1];  in do_tr()
1047 		if (!(opcode & OPCODE))  in do_tr()
1048 			tcode = (opcode >> 12) & ((1 << 4) - 1);  in do_tr()
1050 		if (__get_user(opcode, (u32 __user *)epc))  in do_tr()
1053 		if (!(opcode & OPCODE))  in do_tr()
1054 			tcode = (opcode >> 6) & ((1 << 10) - 1);  in do_tr()
1075 	unsigned int opcode = 0;  in do_ri()  local
1084 	    likely(get_user(opcode, epc) >= 0)) {  in do_ri()
1087 		status = mipsr2_decoder(regs, opcode, &fcr31);  in do_ri()
1125 		opcode = (mmop[0] << 16) | mmop[1];  in do_ri()
1128 			status = simulate_rdhwr_mm(regs, opcode);  in do_ri()
1130 		if (unlikely(get_user(opcode, epc) < 0))  in do_ri()
1134 			status = simulate_llsc(regs, opcode);  in do_ri()
1137 			status = simulate_rdhwr_normal(regs, opcode);  in do_ri()
1140 			status = simulate_sync(regs, opcode);  in do_ri()
1143 			status = simulate_fp(regs, opcode, old_epc, old31);  in do_ri()
1347 	unsigned int opcode;  in do_cpu()  local
1365 		opcode = 0;  in do_cpu()
1378 			opcode = (mmop[0] << 16) | mmop[1];  in do_cpu()
1381 				status = simulate_rdhwr_mm(regs, opcode);  in do_cpu()
1383 			if (unlikely(get_user(opcode, epc) < 0))  in do_cpu()
1387 				status = simulate_llsc(regs, opcode);  in do_cpu()
1390 				status = simulate_rdhwr_normal(regs, opcode);  in do_cpu()