908 	unsigned long vaddr;  in mipsr2_decoder()  local
1201 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1202 		if (!access_ok(VERIFY_READ, vaddr, 4)) {  in mipsr2_decoder()
1203 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1262 			  "+&r"(vaddr), "+&r"(err)  in mipsr2_decoder()
1274 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1275 		if (!access_ok(VERIFY_READ, vaddr, 4)) {  in mipsr2_decoder()
1276 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1337 			  "+&r"(vaddr), "+&r"(err)  in mipsr2_decoder()
1348 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1349 		if (!access_ok(VERIFY_WRITE, vaddr, 4)) {  in mipsr2_decoder()
1350 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1408 			  "+&r"(vaddr), "+&r"(err)  in mipsr2_decoder()
1418 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1419 		if (!access_ok(VERIFY_WRITE, vaddr, 4)) {  in mipsr2_decoder()
1420 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1478 			  "+&r"(vaddr), "+&r"(err)  in mipsr2_decoder()
1493 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1494 		if (!access_ok(VERIFY_READ, vaddr, 8)) {  in mipsr2_decoder()
1495 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1597 			  "+&r"(vaddr), "+&r"(err)  in mipsr2_decoder()
1612 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1613 		if (!access_ok(VERIFY_READ, vaddr, 8)) {  in mipsr2_decoder()
1614 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1716 			  "+&r"(vaddr), "+&r"(err)  in mipsr2_decoder()
1731 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1732 		if (!access_ok(VERIFY_WRITE, vaddr, 8)) {  in mipsr2_decoder()
1733 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1835 			  "+&r"(vaddr), "+&r"(err)  in mipsr2_decoder()
1849 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1850 		if (!access_ok(VERIFY_WRITE, vaddr, 8)) {  in mipsr2_decoder()
1851 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1953 			  "+&r"(vaddr), "+&r"(err)  in mipsr2_decoder()
1961 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1962 		if (vaddr & 0x3) {  in mipsr2_decoder()
1963 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1967 		if (!access_ok(VERIFY_READ, vaddr, 4)) {  in mipsr2_decoder()
1968 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
2007 			: "r"(vaddr), "i"(SIGSEGV)  in mipsr2_decoder()
2017 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
2018 		if (vaddr & 0x3) {  in mipsr2_decoder()
2019 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
2023 		if (!access_ok(VERIFY_WRITE, vaddr, 4)) {  in mipsr2_decoder()
2024 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
2065 			: "r"(vaddr), "i"(SIGSEGV));  in mipsr2_decoder()
2080 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
2081 		if (vaddr & 0x7) {  in mipsr2_decoder()
2082 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
2086 		if (!access_ok(VERIFY_READ, vaddr, 8)) {  in mipsr2_decoder()
2087 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
2126 			: "r"(vaddr), "i"(SIGSEGV)  in mipsr2_decoder()
2141 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
2142 		if (vaddr & 0x7) {  in mipsr2_decoder()
2143 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
2147 		if (!access_ok(VERIFY_WRITE, vaddr, 8)) {  in mipsr2_decoder()
2148 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
2189 			: "r"(vaddr), "i"(SIGSEGV));  in mipsr2_decoder()