Lines Matching refs:uint64_t

31 static inline uint64_t CVMX_SMIX_CLK(unsigned long offset)  in CVMX_SMIX_CLK()
53 static inline uint64_t CVMX_SMIX_CMD(unsigned long offset)  in CVMX_SMIX_CMD()
75 static inline uint64_t CVMX_SMIX_EN(unsigned long offset)  in CVMX_SMIX_EN()
97 static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset)  in CVMX_SMIX_RD_DAT()
119 static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset)  in CVMX_SMIX_WR_DAT()
142 	uint64_t u64;
145 		uint64_t reserved_25_63:39;
146 		uint64_t mode:1;
147 		uint64_t reserved_21_23:3;
148 		uint64_t sample_hi:5;
149 		uint64_t sample_mode:1;
150 		uint64_t reserved_14_14:1;
151 		uint64_t clk_idle:1;
152 		uint64_t preamble:1;
153 		uint64_t sample:4;
154 		uint64_t phase:8;
156 		uint64_t phase:8;
157 		uint64_t sample:4;
158 		uint64_t preamble:1;
159 		uint64_t clk_idle:1;
160 		uint64_t reserved_14_14:1;
161 		uint64_t sample_mode:1;
162 		uint64_t sample_hi:5;
163 		uint64_t reserved_21_23:3;
164 		uint64_t mode:1;
165 		uint64_t reserved_25_63:39;
170 		uint64_t reserved_21_63:43;
171 		uint64_t sample_hi:5;
172 		uint64_t sample_mode:1;
173 		uint64_t reserved_14_14:1;
174 		uint64_t clk_idle:1;
175 		uint64_t preamble:1;
176 		uint64_t sample:4;
177 		uint64_t phase:8;
179 		uint64_t phase:8;
180 		uint64_t sample:4;
181 		uint64_t preamble:1;
182 		uint64_t clk_idle:1;
183 		uint64_t reserved_14_14:1;
184 		uint64_t sample_mode:1;
185 		uint64_t sample_hi:5;
186 		uint64_t reserved_21_63:43;
209 	uint64_t u64;
212 		uint64_t reserved_18_63:46;
213 		uint64_t phy_op:2;
214 		uint64_t reserved_13_15:3;
215 		uint64_t phy_adr:5;
216 		uint64_t reserved_5_7:3;
217 		uint64_t reg_adr:5;
219 		uint64_t reg_adr:5;
220 		uint64_t reserved_5_7:3;
221 		uint64_t phy_adr:5;
222 		uint64_t reserved_13_15:3;
223 		uint64_t phy_op:2;
224 		uint64_t reserved_18_63:46;
229 		uint64_t reserved_17_63:47;
230 		uint64_t phy_op:1;
231 		uint64_t reserved_13_15:3;
232 		uint64_t phy_adr:5;
233 		uint64_t reserved_5_7:3;
234 		uint64_t reg_adr:5;
236 		uint64_t reg_adr:5;
237 		uint64_t reserved_5_7:3;
238 		uint64_t phy_adr:5;
239 		uint64_t reserved_13_15:3;
240 		uint64_t phy_op:1;
241 		uint64_t reserved_17_63:47;
264 	uint64_t u64;
267 		uint64_t reserved_1_63:63;
268 		uint64_t en:1;
270 		uint64_t en:1;
271 		uint64_t reserved_1_63:63;
295 	uint64_t u64;
298 		uint64_t reserved_18_63:46;
299 		uint64_t pending:1;
300 		uint64_t val:1;
301 		uint64_t dat:16;
303 		uint64_t dat:16;
304 		uint64_t val:1;
305 		uint64_t pending:1;
306 		uint64_t reserved_18_63:46;
330 	uint64_t u64;
333 		uint64_t reserved_18_63:46;
334 		uint64_t pending:1;
335 		uint64_t val:1;
336 		uint64_t dat:16;
338 		uint64_t dat:16;
339 		uint64_t val:1;
340 		uint64_t pending:1;
341 		uint64_t reserved_18_63:46;