Lines Matching refs:MIPS_CM_GCB_OFS
104 #define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */ macro
186 BUILD_CM_R_(config, MIPS_CM_GCB_OFS + 0x00)
187 BUILD_CM_RW(base, MIPS_CM_GCB_OFS + 0x08)
188 BUILD_CM_RW(access, MIPS_CM_GCB_OFS + 0x20)
189 BUILD_CM_R_(rev, MIPS_CM_GCB_OFS + 0x30)
190 BUILD_CM_RW(error_mask, MIPS_CM_GCB_OFS + 0x40)
191 BUILD_CM_RW(error_cause, MIPS_CM_GCB_OFS + 0x48)
192 BUILD_CM_RW(error_addr, MIPS_CM_GCB_OFS + 0x50)
193 BUILD_CM_RW(error_mult, MIPS_CM_GCB_OFS + 0x58)
194 BUILD_CM_RW(l2_only_sync_base, MIPS_CM_GCB_OFS + 0x70)
195 BUILD_CM_RW(gic_base, MIPS_CM_GCB_OFS + 0x80)
196 BUILD_CM_RW(cpc_base, MIPS_CM_GCB_OFS + 0x88)
197 BUILD_CM_RW(reg0_base, MIPS_CM_GCB_OFS + 0x90)
198 BUILD_CM_RW(reg0_mask, MIPS_CM_GCB_OFS + 0x98)
199 BUILD_CM_RW(reg1_base, MIPS_CM_GCB_OFS + 0xa0)
200 BUILD_CM_RW(reg1_mask, MIPS_CM_GCB_OFS + 0xa8)
201 BUILD_CM_RW(reg2_base, MIPS_CM_GCB_OFS + 0xb0)
202 BUILD_CM_RW(reg2_mask, MIPS_CM_GCB_OFS + 0xb8)
203 BUILD_CM_RW(reg3_base, MIPS_CM_GCB_OFS + 0xc0)
204 BUILD_CM_RW(reg3_mask, MIPS_CM_GCB_OFS + 0xc8)
205 BUILD_CM_R_(gic_status, MIPS_CM_GCB_OFS + 0xd0)
206 BUILD_CM_R_(cpc_status, MIPS_CM_GCB_OFS + 0xf0)
207 BUILD_CM_RW(l2_config, MIPS_CM_GCB_OFS + 0x130)
208 BUILD_CM_RW(sys_config2, MIPS_CM_GCB_OFS + 0x150)
209 BUILD_CM_RW(l2_pft_control, MIPS_CM_GCB_OFS + 0x300)
210 BUILD_CM_RW(l2_pft_control_b, MIPS_CM_GCB_OFS + 0x308)