Lines Matching refs:BIT
203 #define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
233 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
234 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
235 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
242 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
243 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
244 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
268 #define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
269 #define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
270 #define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
277 #define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
278 #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
279 #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
324 #define MISC_INT_ETHSW BIT(12)
325 #define MISC_INT_TIMER4 BIT(10)
326 #define MISC_INT_TIMER3 BIT(9)
327 #define MISC_INT_TIMER2 BIT(8)
328 #define MISC_INT_DMA BIT(7)
329 #define MISC_INT_OHCI BIT(6)
330 #define MISC_INT_PERFC BIT(5)
331 #define MISC_INT_WDOG BIT(4)
332 #define MISC_INT_UART BIT(3)
333 #define MISC_INT_GPIO BIT(2)
334 #define MISC_INT_ERROR BIT(1)
335 #define MISC_INT_TIMER BIT(0)
337 #define AR71XX_RESET_EXTERNAL BIT(28)
338 #define AR71XX_RESET_FULL_CHIP BIT(24)
339 #define AR71XX_RESET_CPU_NMI BIT(21)
340 #define AR71XX_RESET_CPU_COLD BIT(20)
341 #define AR71XX_RESET_DMA BIT(19)
342 #define AR71XX_RESET_SLIC BIT(18)
343 #define AR71XX_RESET_STEREO BIT(17)
344 #define AR71XX_RESET_DDR BIT(16)
345 #define AR71XX_RESET_GE1_MAC BIT(13)
346 #define AR71XX_RESET_GE1_PHY BIT(12)
347 #define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)
348 #define AR71XX_RESET_GE0_MAC BIT(9)
349 #define AR71XX_RESET_GE0_PHY BIT(8)
350 #define AR71XX_RESET_USB_OHCI_DLL BIT(6)
351 #define AR71XX_RESET_USB_HOST BIT(5)
352 #define AR71XX_RESET_USB_PHY BIT(4)
353 #define AR71XX_RESET_PCI_BUS BIT(1)
354 #define AR71XX_RESET_PCI_CORE BIT(0)
356 #define AR7240_RESET_USB_HOST BIT(5)
357 #define AR7240_RESET_OHCI_DLL BIT(3)
359 #define AR724X_RESET_GE1_MDIO BIT(23)
360 #define AR724X_RESET_GE0_MDIO BIT(22)
361 #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
362 #define AR724X_RESET_PCIE_PHY BIT(7)
363 #define AR724X_RESET_PCIE BIT(6)
364 #define AR724X_RESET_USB_HOST BIT(5)
365 #define AR724X_RESET_USB_PHY BIT(4)
366 #define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
368 #define AR913X_RESET_AMBA2WMAC BIT(22)
369 #define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
370 #define AR913X_RESET_USB_HOST BIT(5)
371 #define AR913X_RESET_USB_PHY BIT(4)
373 #define AR933X_RESET_WMAC BIT(11)
374 #define AR933X_RESET_USB_HOST BIT(5)
375 #define AR933X_RESET_USB_PHY BIT(4)
376 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
378 #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
379 #define AR934X_RESET_USB_HOST BIT(5)
380 #define AR934X_RESET_USB_PHY BIT(4)
381 #define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
383 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
385 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
386 #define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
387 #define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
388 #define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
389 #define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
390 #define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
391 #define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
392 #define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
393 #define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
394 #define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
395 #define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
396 #define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
397 #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
398 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
399 #define AR934X_BOOTSTRAP_DDR1 BIT(0)
401 #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
403 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
404 #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
405 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
406 #define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
407 #define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
408 #define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
409 #define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
410 #define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
411 #define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
421 #define QCA955X_EXT_INT_WMAC_MISC BIT(0)
422 #define QCA955X_EXT_INT_WMAC_TX BIT(1)
423 #define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
424 #define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
425 #define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
426 #define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
427 #define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
428 #define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
429 #define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
430 #define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
431 #define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
432 #define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
433 #define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
434 #define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
435 #define QCA955X_EXT_INT_USB1 BIT(24)
436 #define QCA955X_EXT_INT_USB2 BIT(28)
495 #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
497 #define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */
500 #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
501 #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
502 #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
551 #define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)