Lines Matching refs:cvmx_write_csr
275 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); in octeon_irq_ciu_enable()
284 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); in octeon_irq_ciu_enable()
307 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); in octeon_irq_ciu_enable_local()
316 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); in octeon_irq_ciu_enable_local()
339 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); in octeon_irq_ciu_disable_local()
348 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); in octeon_irq_ciu_disable_local()
379 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); in octeon_irq_ciu_disable_all()
381 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); in octeon_irq_ciu_disable_all()
412 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); in octeon_irq_ciu_enable_all()
414 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); in octeon_irq_ciu_enable_all()
439 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); in octeon_irq_ciu_enable_v2()
443 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); in octeon_irq_ciu_enable_v2()
460 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask); in octeon_irq_ciu_enable_sum2()
476 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask); in octeon_irq_ciu_disable_local_sum2()
489 cvmx_write_csr(CVMX_CIU_SUM2_PPX_IP4(index), mask); in octeon_irq_ciu_ack_sum2()
504 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(coreid), mask); in octeon_irq_ciu_disable_all_sum2()
523 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); in octeon_irq_ciu_enable_local_v2()
527 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); in octeon_irq_ciu_enable_local_v2()
542 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); in octeon_irq_ciu_disable_local_v2()
546 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); in octeon_irq_ciu_disable_local_v2()
563 cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask); in octeon_irq_ciu_ack()
565 cvmx_write_csr(CVMX_CIU_INT_SUM1, mask); in octeon_irq_ciu_ack()
587 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); in octeon_irq_ciu_disable_all_v2()
594 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); in octeon_irq_ciu_disable_all_v2()
617 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); in octeon_irq_ciu_enable_all_v2()
624 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); in octeon_irq_ciu_enable_all_v2()
646 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), cfg.u64); in octeon_irq_gpio_setup()
679 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); in octeon_irq_ciu_disable_gpio_v2()
689 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); in octeon_irq_ciu_disable_gpio()
702 cvmx_write_csr(CVMX_GPIO_INT_CLR, mask); in octeon_irq_ciu_gpio_ack()
779 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); in octeon_irq_ciu_set_affinity()
781 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); in octeon_irq_ciu_set_affinity()
814 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); in octeon_irq_ciu_set_affinity_v2()
817 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); in octeon_irq_ciu_set_affinity_v2()
827 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); in octeon_irq_ciu_set_affinity_v2()
830 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); in octeon_irq_ciu_set_affinity_v2()
857 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask); in octeon_irq_ciu_set_affinity_sum2()
859 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask); in octeon_irq_ciu_set_affinity_sum2()
1022 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); in octeon_irq_ciu_wd_enable()
1036 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(coreid * 2 + 1), 1ull << coreid); in octeon_irq_ciu1_wd_enable_v2()
1349 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); in octeon_irq_init_ciu_percpu()
1350 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); in octeon_irq_init_ciu_percpu()
1351 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); in octeon_irq_init_ciu_percpu()
1352 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); in octeon_irq_init_ciu_percpu()
1372 cvmx_write_csr(base + regx + ipx, 0); in octeon_irq_init_ciu2_percpu()
1608 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_wd_enable()
1625 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_enable()
1640 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_enable_local()
1656 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_disable_local()
1671 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_ack()
1687 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_disable_all()
1701 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_mbox_enable_all()
1715 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_mbox_disable_all()
1727 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_mbox_enable_local()
1738 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_mbox_disable_local()
1768 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_set_affinity()
1787 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); in octeon_irq_ciu2_disable_gpio()
2096 cvmx_write_csr(host_data->en_reg, en); in octeon_irq_cib_enable()
2110 cvmx_write_csr(host_data->en_reg, en); in octeon_irq_cib_disable()
2214 cvmx_write_csr(host_data->en_reg, en); in octeon_irq_cib_handler()
2215 cvmx_write_csr(host_data->raw_reg, 1ull << i); in octeon_irq_cib_handler()
2223 cvmx_write_csr(host_data->raw_reg, 1ull << i); in octeon_irq_cib_handler()
2283 cvmx_write_csr(host_data->en_reg, 0); /* disable all IRQs */ in octeon_irq_init_cib()
2284 cvmx_write_csr(host_data->raw_reg, ~0); /* ack any outstanding */ in octeon_irq_init_cib()