Lines Matching refs:alchemy_rdsys
130 t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f; in alchemy_clk_cpu_recalc()
183 return (alchemy_rdsys(a->reg) & 0xff) * parent_rate; in alchemy_clk_aux_recalc()
267 unsigned long v = (alchemy_rdsys(AU1000_SYS_POWERCTRL) & 3) + 2; in alchemy_clk_setup_sysbus()
489 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_en()
500 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1); in alchemy_clk_fgv1_isen()
511 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_dis()
523 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_setp()
538 return (alchemy_rdsys(c->reg) >> c->shift) & 1; in alchemy_clk_fgv1_getp()
552 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_setr()
565 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2); in alchemy_clk_fgv1_recalc()
591 unsigned long v = alchemy_rdsys(c->reg); in __alchemy_clk_fgv2_en()
616 return ((alchemy_rdsys(c->reg) >> c->shift) & 3) != 0; in alchemy_clk_fgv2_isen()
625 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv2_dis()
672 v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */ in alchemy_clk_fgv2_setr()
677 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv2_setr()
693 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv2_recalc()
707 if (alchemy_rdsys(c->reg) & (1 << 30)) { in alchemy_clk_fgv2_detr()
788 v = alchemy_rdsys(a->reg); in alchemy_clk_init_fgens()
814 unsigned long v = alchemy_rdsys(c->reg); in alchemy_clk_csrc_isen()
821 unsigned long v = alchemy_rdsys(c->reg); in __alchemy_clk_csrc_en()
848 v = alchemy_rdsys(c->reg); in alchemy_clk_csrc_dis()
880 unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3; in alchemy_clk_csrc_recalc()
909 v = alchemy_rdsys(c->reg); in alchemy_clk_csrc_setr()
1007 v = alchemy_rdsys(a->reg); in alchemy_clk_setup_imux()