Lines Matching refs:r6

94 		lwi	r6, r1, PT_R6;		\
340 	swi	r6, r1, PT_R6
369 	addk	r6, r5, r5; /* << 1 */
370 	addk	r6, r6, r6; /* << 2 */
377 	lwi	r5, r6, TOPHYS(exception_debug_table)
379 	swi	r5, r6, TOPHYS(exception_debug_table)
383 	lwi	r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable)
384 	bra	r6
391 	mfs	r6, rmsr;
393 	swi	r6, r1, 0; /* RMSR_OFFSET */
394 	ori	r6, r6, 0x100; /* Turn ON the EE bit */
395 	andi	r6, r6, ~2; /* Disable interrupts */
396 	mts	rmsr, r6;
399 	xori	r6, r5, 1; /* 00001 = Unaligned Exception */
401 	beqi	r6, handle_unaligned_ex;
416 	andi	r6, r4, 0x1F; /* Load ESR[EC] */
470 	andi	r6, r4, 0x1000			/* Check ESR[DS] */
471 	beqi	r6, _no_delayslot		/* Branch if ESR[DS] not set */
479 	andi	r6, r4, 0x3E0; /* Mask and extract the register operand */
480 	srl	r6, r6; /* r6 >> 5 */
481 	srl	r6, r6;
482 	srl	r6, r6;
483 	srl	r6, r6;
484 	srl	r6, r6;
486 	sbi	r6, r0, TOPHYS(ex_reg_op);
488 	andi	r6, r4, 0x400; /* Extract ESR[S] */
489 	bnei	r6, ex_sw;
491 	andi	r6, r4, 0x800; /* Extract ESR[W] */
492 	beqi	r6, ex_lhw;
519 	addik	r6, r0, TOPHYS(lw_table);
523 	addk	r5, r5, r6;
530 	addik	r6, r0, TOPHYS(sw_table);
534 	add	r5, r5, r6;
537 	mfs	r6, resr;
539 	andi	r6, r6, 0x800; /* Extract ESR[W] */
540 	beqi	r6, ex_shw;
571 	lwi	r6, r1, PT_R6
641 		bsrli	r6, r3, PTE_SHIFT /* Compute PTE address */
642 		andi	r6, r6, PAGE_SIZE - 4
643 		or	r5, r5, r6
646 		andi	r6, r4, _PAGE_RW	/* Is it writeable? */
647 		beqi	r6, ex2			/* Bail if not */
717 		ori	r6, r0, CONFIG_KERNEL_START
718 		cmpu	r4, r3, r6
742 		bsrli	r6, r3, PTE_SHIFT /* Compute PTE address */
743 		andi	r6, r6, PAGE_SIZE - 4
744 		or	r5, r5, r6
747 		andi	r6, r4, _PAGE_PRESENT
748 		beqi	r6, ex7
813 		bsrli	r6, r3, PTE_SHIFT /* Compute PTE address */
814 		andi	r6, r6, PAGE_SIZE - 4
815 		or	r5, r5, r6
818 		andi	r6, r4, _PAGE_PRESENT
819 		beqi	r6, ex10
869 		ori	r6, r0, 1
870 		cmp	r31, r5, r6
951 	andi	r6, r3, 0x400;	/* Extract ESR[S] */
952 	bneid	r6, ex_sw_vm;
953 	andi	r6, r3, 0x800;	/* Extract ESR[W] - delay slot */
955 	beqid	r6, ex_lhw_vm;
958 	addik	r6, r0, ex_tmp_data_loc_0;
959 	sbi	r5, r6, 0;
961 	sbi	r5, r6, 1;
963 	sbi	r5, r6, 2;
965 	sbi	r5, r6, 3;
968 	lwi	r3, r6, 0;
972 	addik	r6, r0, ex_tmp_data_loc_0;
973 	sbi	r5, r6, 0;
975 	sbi	r5, r6, 1;
976 	lhui	r3, r6, 0;	/* Get the destination register value into r3 */
989 	beqid	r6, ex_shw_vm;
1025 	lwi	r6, r7, PT_PC; /* faulting address is one instruction above */
1026 	addik	r6, r6, -4 /* for finding proper fixup */
1027 	swi	r6, r7, PT_PC; /* a save back it to PT_PC */