Lines Matching refs:r11
35 mfs r11, rmsr
36 andi r11, r11, ~MSR_IE
37 mts rmsr, r11
41 mfs r11, rmsr
42 ori r11, r11, MSR_IE
43 mts rmsr, r11
47 mfs r11, rmsr
48 andi r11, r11, ~MSR_BIP
49 mts rmsr, r11
55 swi r11, r0, PER_CPU(R11_SAVE) /* temporarily save r11 */
56 lwi r11, r0, PER_CPU(KM) /* load mode indicator */
57 beqid r11, 1f
67 swi r11, r1, PT_MODE /* store the mode */
68 lwi r11, r0, PER_CPU(R11_SAVE) /* reload r11 */
78 swi r11, r1, PT_R11
101 mfs r11, rmsr
102 swi r11, r1, PT_MSR
103 mfs r11, rear
104 swi r11, r1, PT_EAR
105 mfs r11, resr
106 swi r11, r1, PT_ESR
107 mfs r11, rfsr
108 swi r11, r1, PT_FSR
110 lwi r11, r0, PER_CPU(ENTRY_SP)
111 swi r11, r1, PT_R1
113 addik r11, r0, 1
114 swi r11, r0, PER_CPU(KM)
124 lwi r11, r1, PT_MODE
125 bneid r11, no_intr_resched
132 andi r11, r19, _TIF_NEED_RESCHED
133 beqi r11, 1f
137 1: andi r11, r19, _TIF_SIGPENDING | _TIF_NOTIFY_RESUME
138 beqid r11, no_intr_resched
149 lwi r11, r1, PT_MODE
150 swi r11, r0, PER_CPU(KM)
156 lwi r11, r1, PT_FSR
157 mts rfsr, r11
158 lwi r11, r1, PT_ESR
159 mts resr, r11
160 lwi r11, r1, PT_EAR
161 mts rear, r11
162 lwi r11, r1, PT_MSR
163 mts rmsr, r11
185 lwi r11, r1, PT_R11
204 swi r11, r0, PER_CPU(R11_SAVE) /* temporarily save r11 */
205 lwi r11, r0, PER_CPU(KM) /* load mode indicator */
206 beqid r11, 1f /* Already in kernel mode? */
216 swi r11, r1, PT_MODE /* store the mode */
217 lwi r11, r0, PER_CPU(R11_SAVE) /* reload r11 */
228 swi r11, r1, PT_R11
261 mfs r11, rmsr
262 swi r11, r1, PT_MSR
263 mfs r11, rear
264 swi r11, r1, PT_EAR
265 mfs r11, resr
266 swi r11, r1, PT_ESR
267 mfs r11, rfsr
268 swi r11, r1, PT_FSR
270 lwi r11, r0, PER_CPU(ENTRY_SP)
271 swi r11, r1, PT_R1
273 addik r11, r0, 1
274 swi r11, r0, PER_CPU(KM)
281 addi r11, r12, -__NR_syscalls
282 bgei r11, 1f /* return to user if not valid */
306 swi r11, r0, PER_CPU(R11_SAVE) /* temporarily save r11 */
307 lwi r11, r0, PER_CPU(KM) /* load mode indicator */
309 swi r11, r1, PT_MODE /* store the mode */
310 lwi r11, r0, PER_CPU(R11_SAVE) /* reload r11 */
321 swi r11, r1, PT_R11
352 mfs r11, rmsr
353 swi r11, r1, PT_MSR
354 mfs r11, rear
355 swi r11, r1, PT_EAR
356 mfs r11, resr
357 swi r11, r1, PT_ESR
358 mfs r11, rfsr
359 swi r11, r1, PT_FSR
361 lwi r11, r0, PER_CPU(ENTRY_SP)
362 swi r11, r1, PT_R1
364 addik r11, r0, 1
365 swi r11, r0, PER_CPU(KM)
393 addik r11, r5, TI_CPU_CONTEXT
394 swi r1, r11, CC_R1
395 swi r2, r11, CC_R2
399 swi r13, r11, CC_R13
400 swi r14, r11, CC_R14
401 swi r15, r11, CC_R15
402 swi r16, r11, CC_R16
403 swi r17, r11, CC_R17
404 swi r18, r11, CC_R18
406 swi r19, r11, CC_R19
407 swi r20, r11, CC_R20
408 swi r21, r11, CC_R21
409 swi r22, r11, CC_R22
410 swi r23, r11, CC_R23
411 swi r24, r11, CC_R24
412 swi r25, r11, CC_R25
413 swi r26, r11, CC_R26
414 swi r27, r11, CC_R27
415 swi r28, r11, CC_R28
416 swi r29, r11, CC_R29
417 swi r30, r11, CC_R30
420 swi r12, r11, CC_MSR
422 swi r12, r11, CC_EAR
424 swi r12, r11, CC_ESR
426 swi r12, r11, CC_FSR
433 addik r11, r6, TI_CPU_CONTEXT
436 lwi r12, r11, CC_FSR
438 lwi r12, r11, CC_ESR
440 lwi r12, r11, CC_EAR
442 lwi r12, r11, CC_MSR
445 lwi r30, r11, CC_R30
446 lwi r29, r11, CC_R29
447 lwi r28, r11, CC_R28
448 lwi r27, r11, CC_R27
449 lwi r26, r11, CC_R26
450 lwi r25, r11, CC_R25
451 lwi r24, r11, CC_R24
452 lwi r23, r11, CC_R23
453 lwi r22, r11, CC_R22
454 lwi r21, r11, CC_R21
455 lwi r20, r11, CC_R20
456 lwi r19, r11, CC_R19
458 lwi r18, r11, CC_R18
459 lwi r17, r11, CC_R17
460 lwi r16, r11, CC_R16
461 lwi r15, r11, CC_R15
462 lwi r14, r11, CC_R14
463 lwi r13, r11, CC_R13
465 lwi r2, r11, CC_R2
466 lwi r1, r11, CC_R1
490 lwi r11, r1, PT_MODE
491 bneid r11, 2f
494 andi r11, r19, _TIF_NEED_RESCHED
495 beqi r11, 1f
499 1: andi r11, r19, _TIF_SIGPENDING | _TIF_NOTIFY_RESUME
500 beqi r11, no_work_pending
560 lwi r11, r1, PT_R11