Lines Matching refs:MCF_MBAR

19 #define MCFICM_INTC0		(MCF_MBAR + 0x700) 	/* Base for Interrupt Ctrl 0 */
34 #define MCFUART_BASE0		(MCF_MBAR + 0x8600)	/* Base address UART0 */
35 #define MCFUART_BASE1		(MCF_MBAR + 0x8700)	/* Base address UART1 */
36 #define MCFUART_BASE2		(MCF_MBAR + 0x8800)	/* Base address UART2 */
37 #define MCFUART_BASE3		(MCF_MBAR + 0x8900)	/* Base address UART3 */
52 #define MCFSLT_TIMER0		(MCF_MBAR + 0x900)	/* Base addr TIMER0 */
53 #define MCFSLT_TIMER1		(MCF_MBAR + 0x910)	/* Base addr TIMER1 */
58 #define MCFGPIO_PODR		(MCF_MBAR + 0xA00)
59 #define MCFGPIO_PDDR		(MCF_MBAR + 0xA10)
60 #define MCFGPIO_PPDR		(MCF_MBAR + 0xA20)
61 #define MCFGPIO_SETR		(MCF_MBAR + 0xA20)
62 #define MCFGPIO_CLRR		(MCF_MBAR + 0xA30)
71 #define	MCFEPORT_EPPAR		(MCF_MBAR + 0xf00)	/* Pin assignment */
72 #define	MCFEPORT_EPDDR		(MCF_MBAR + 0xf04)	/* Data direction */
73 #define	MCFEPORT_EPIER		(MCF_MBAR + 0xf05)	/* Interrupt enable */
74 #define	MCFEPORT_EPDR		(MCF_MBAR + 0xf08)	/* Port data (w) */
75 #define	MCFEPORT_EPPDR		(MCF_MBAR + 0xf09)	/* Port data (r) */
76 #define	MCFEPORT_EPFR		(MCF_MBAR + 0xf0c)	/* Flags */
81 #define MCFGPIO_PAR_FBCTL	(MCF_MBAR + 0xA40)
82 #define MCFGPIO_PAR_FBCS	(MCF_MBAR + 0xA42)
83 #define MCFGPIO_PAR_DMA		(MCF_MBAR + 0xA43)
84 #define MCFGPIO_PAR_FECI2CIRQ	(MCF_MBAR + 0xA44)
85 #define MCFGPIO_PAR_PCIBG	(MCF_MBAR + 0xA48)	/* PCI bus grant */
86 #define MCFGPIO_PAR_PCIBR	(MCF_MBAR + 0xA4A)	/* PCI */
87 #define MCFGPIO_PAR_PSC0	(MCF_MBAR + 0xA4F)
88 #define MCFGPIO_PAR_PSC1	(MCF_MBAR + 0xA4E)
89 #define MCFGPIO_PAR_PSC2	(MCF_MBAR + 0xA4D)
90 #define MCFGPIO_PAR_PSC3	(MCF_MBAR + 0xA4C)
91 #define MCFGPIO_PAR_DSPI	(MCF_MBAR + 0xA50)
92 #define MCFGPIO_PAR_TIMER	(MCF_MBAR + 0xA52)