Lines Matching refs:uint
65 #define CPM_DATAONLY_BASE ((uint)0x0000)
66 #define CPM_DATAONLY_SIZE ((uint)0x0800)
67 #define CPM_DP_NOSPACE ((uint)0x7fffffff)
76 uint m360_cpm_dpalloc(uint size);
78 void m360_cpm_setbrg(uint brg, uint rate);
85 uint cbd_bufaddr; /* Buffer address in host memory */
159 uint smc_rstate; /* Internal */
160 uint smc_idp; /* Internal */
163 uint smc_rxtmp; /* Internal */
164 uint smc_tstate; /* Internal */
165 uint smc_tdp; /* Internal */
168 uint smc_txtmp; /* Internal */
209 uint scent_rstate;
210 uint scent_r_ptr;
213 uint scent_rtemp;
214 uint scent_tstate;
215 uint scent_t_ptr;
218 uint scent_ttemp;
250 #define CPM_BRG_RST ((uint)0x00020000)
251 #define CPM_BRG_EN ((uint)0x00010000)
252 #define CPM_BRG_EXTC_INT ((uint)0x00000000)
253 #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
254 #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
255 #define CPM_BRG_ATB ((uint)0x00002000)
256 #define CPM_BRG_CD_MASK ((uint)0x00001ffe)
257 #define CPM_BRG_DIV16 ((uint)0x00000001)
261 #define SCC_GSMRH_IRP ((uint)0x00040000)
262 #define SCC_GSMRH_GDE ((uint)0x00010000)
263 #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
264 #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
265 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
266 #define SCC_GSMRH_REVD ((uint)0x00002000)
267 #define SCC_GSMRH_TRX ((uint)0x00001000)
268 #define SCC_GSMRH_TTX ((uint)0x00000800)
269 #define SCC_GSMRH_CDP ((uint)0x00000400)
270 #define SCC_GSMRH_CTSP ((uint)0x00000200)
271 #define SCC_GSMRH_CDS ((uint)0x00000100)
272 #define SCC_GSMRH_CTSS ((uint)0x00000080)
273 #define SCC_GSMRH_TFL ((uint)0x00000040)
274 #define SCC_GSMRH_RFW ((uint)0x00000020)
275 #define SCC_GSMRH_TXSY ((uint)0x00000010)
276 #define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
277 #define SCC_GSMRH_SYNL8 ((uint)0x00000008)
278 #define SCC_GSMRH_SYNL4 ((uint)0x00000004)
279 #define SCC_GSMRH_RTSM ((uint)0x00000002)
280 #define SCC_GSMRH_RSYN ((uint)0x00000001)
282 #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
283 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
284 #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
285 #define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
286 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
287 #define SCC_GSMRL_TCI ((uint)0x10000000)
288 #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
289 #define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
290 #define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
291 #define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
292 #define SCC_GSMRL_RINV ((uint)0x02000000)
293 #define SCC_GSMRL_TINV ((uint)0x01000000)
294 #define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
295 #define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
296 #define SCC_GSMRL_TPL_48 ((uint)0x00800000)
297 #define SCC_GSMRL_TPL_32 ((uint)0x00600000)
298 #define SCC_GSMRL_TPL_16 ((uint)0x00400000)
299 #define SCC_GSMRL_TPL_8 ((uint)0x00200000)
300 #define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
301 #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
302 #define SCC_GSMRL_TPP_01 ((uint)0x00100000)
303 #define SCC_GSMRL_TPP_10 ((uint)0x00080000)
304 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
305 #define SCC_GSMRL_TEND ((uint)0x00040000)
306 #define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
307 #define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
308 #define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
309 #define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
310 #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
311 #define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
312 #define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
313 #define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
314 #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
315 #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
316 #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
317 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
318 #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
319 #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
320 #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
321 #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
322 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
323 #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
324 #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
325 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
326 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
327 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
328 #define SCC_GSMRL_ENR ((uint)0x00000020)
329 #define SCC_GSMRL_ENT ((uint)0x00000010)
330 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
331 #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
332 #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
333 #define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
334 #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
335 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
336 #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
337 #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
338 #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
339 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
356 uint scc_rstate; /* Internal */
357 uint scc_idp; /* Internal */
360 uint scc_rxtmp; /* Internal */
361 uint scc_tstate; /* Internal */
362 uint scc_tdp; /* Internal */
365 uint scc_txtmp; /* Internal */
366 uint scc_rcrc; /* Internal */
367 uint scc_tcrc; /* Internal */
380 uint sen_cpres; /* Preset CRC */
381 uint sen_cmask; /* Constant mask for CRC */
382 uint sen_crcec; /* CRC Error counter */
383 uint sen_alec; /* alignment error counter */
384 uint sen_disfc; /* discard frame counter */
399 uint sen_tbuf0data0; /* Save area 0 - current frame */
400 uint sen_tbuf0data1; /* Save area 1 - current frame */
401 uint sen_tbuf0rba; /* Internal */
402 uint sen_tbuf0crc; /* Internal */
411 uint sen_tbuf1data0; /* Save area 0 - current frame */
412 uint sen_tbuf1data1; /* Save area 1 - current frame */
413 uint sen_tbuf1rba; /* Internal */
414 uint sen_tbuf1crc; /* Internal */
455 #define SICR_ENET_MASK ((uint)0x000000ff)
456 #define SICR_ENET_CLKRT ((uint)0x0000002c)
479 #define SICR_ENET_MASK ((uint)0x000000ff)
480 #define SICR_ENET_CLKRT ((uint)0x0000003d)
545 uint scc_res1; /* Reserved */
546 uint scc_res2; /* Reserved */
606 uint st_cpres; /* Preset CRC */
607 uint st_cmask; /* Constant mask for CRC */
656 #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
657 #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
658 #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
659 #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
660 #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
661 #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
662 #define CICR_IEN ((uint)0x00000080) /* Int. enable */
663 #define CICR_SPS ((uint)0x00000001) /* SCC Spread */