Lines Matching refs:r1
31 st r1, @-sp
36 ld r1, @(MESTS_offset, r3) ; r1: status (MESTS reg.)
38 st r1, @(MESTS_offset, r3) ; clear status (MESTS reg.)
39 and3 r1, r1, #(MESTS_IT)
40 bnez r1, 1f ; instruction TLB miss?
45 ;; r1 - r3: free
48 ;; r1: TLB entry base address
56 ldi r1, #-8192
59 and r1, sp
60 ld r1, @(16, r1) ; current_thread_info->cpu
61 slli r1, #2
62 add r2, r1
64 seth r1, #high(DTLB_BASE)
65 or3 r1, r1, #low(DTLB_BASE)
74 ;; r1 - r3: free
77 ;; r1: TLB entry base address
82 mvfc r1, bpc
83 and r1, r3
84 or r0, r1 ; r0: PFN + ASID
89 ldi r1, #-8192
92 and r1, sp
93 ld r1, @(16, r1) ; current_thread_info->cpu
94 slli r1, #2
95 add r2, r1
97 seth r1, #high(ITLB_BASE)
98 or3 r1, r1, #low(ITLB_BASE)
105 ;; r1: TLB entry base address
110 ;; r1: TLB entry address
113 ld r3, @r2 || srli r1, #3
116 srli r1, #3
118 add r1, r3
123 st r3, @r2 || slli r1, #3
126 slli r1, #3
132 ;; r1: TLB entry address
136 ;; r1: TLB entry address
178 ;; r1: TLB entry address
181 st r0, @r1 ; set_tlb_tag(entry++, address);
182 st r2, @+r1 ; set_tlb_data(entry, pte_data);
188 ld r1, @sp+
197 ;; r1: TLB entry address
201 ;; r1: TLB entry address
215 st r1, @-sp
223 ld r1, @(MESTS_offset,r3) ; r1: status (MESTS reg.)
224 st r1, @(MESTS_offset,r3) ; clear status (MESTS reg.)
225 and3 r1, r1, #(MESTS_IT)
226 beqz r1, 1f ; data TLB miss?
234 seth r1, #high(ITLB_BASE)
235 or3 r1, r1, #low(ITLB_BASE)
236 add r2, r1 ; r2: entry
248 seth r1, #high(DTLB_BASE)
249 or3 r1, r1, #low(DTLB_BASE)
250 add r2, r1 ; r2: entry
258 ; r1,r3,r4: (free)
260 ld24 r1, #(-MPTB-1)
261 not r1, r1
262 ld r1, @r1
265 add r3, r1 ; r3: pgd
267 ld r1, @r3 ; r1: pmd
268 beqz r1, 3f ; pmd_none(*pmd) ?
270 and3 r1, r1, #0x3ff
272 bne r1, r4, 3f ; pmd_bad(*pmd) ?
286 ld r1, @r4 ; r1: pte_data
287 and3 r3, r1, #2 ; _PAGE_PRESENT(=2) check
292 ; r0: address, r1: pte_data, r2: entry
302 st r1, @(4,r2) ; set_tlb_data(entry, pte_data);
307 ld r1, @sp+
314 ldi r1, #2 ; r1: pte_data = 0 | _PAGE_PRESENT(=2)
325 ldi r1, #0
326 st r1, @(MPSZ_offset,r0) ; Set MPSZ Reg(Page size 4KB:0 16KB:1 64KB:2)
327 ldi r1, #0
328 st r1, @(MASID_offset,r0) ; Set ASID Zero
333 seth r1, #high(DTLB_BASE) ; Set DTLB_BASE higher
334 or3 r1, r1, #low(DTLB_BASE) ; Set DTLB_BASE lower
338 addi r1, #-4
342 st r2, @+r1 ; VPA <- 0
343 st r2, @+r1 ; PPA <- 0