Lines Matching refs:entry1
351 volatile unsigned long *entry1, *entry2; in update_mmu_cache() local
368 entry1 = (unsigned long *)ITLB_BASE; in update_mmu_cache()
370 if (*entry1++ == vaddr) { in update_mmu_cache()
371 set_tlb_data(entry1, pte_data); in update_mmu_cache()
374 entry1++; in update_mmu_cache()
404 : "=&r" (entry1), "=&r" (entry2) in update_mmu_cache()
411 if ((!inst && entry2 >= DTLB_END) || (inst && entry1 >= ITLB_END)) in update_mmu_cache()
433 entry1 = entry2 + (((*entry_dat - 1) & TLB_MASK) << 1); in update_mmu_cache()
436 if (!(entry1[1] & 2)) /* Valid bit check */ in update_mmu_cache()
439 if (entry1 != entry2) in update_mmu_cache()
440 entry1 -= 2; in update_mmu_cache()
442 entry1 += TLB_MASK << 1; in update_mmu_cache()
446 entry1 = entry2 + (*entry_dat << 1); in update_mmu_cache()
449 *entry1++ = vaddr; /* Set TLB tag */ in update_mmu_cache()
450 set_tlb_data(entry1, pte_data); in update_mmu_cache()