Lines Matching refs:MMU_REG_BASE
77 #define MMU_REG_BASE (0xffff0000) macro
83 #define MATM MMU_REG_BASE /* MMU Address Translation Mode
85 #define MPSZ (0x04 + MMU_REG_BASE) /* MMU Page Size Designation Register */
86 #define MASID (0x08 + MMU_REG_BASE) /* MMU Address Space ID Register */
87 #define MESTS (0x0c + MMU_REG_BASE) /* MMU Exception Status Register */
88 #define MDEVA (0x10 + MMU_REG_BASE) /* MMU Operand Exception Virtual
90 #define MDEVP (0x14 + MMU_REG_BASE) /* MMU Operand Exception Virtual Page
92 #define MPTB (0x18 + MMU_REG_BASE) /* MMU Page Table Base Register */
93 #define MSVA (0x20 + MMU_REG_BASE) /* MMU Search Virtual Address
95 #define MTOP (0x24 + MMU_REG_BASE) /* MMU TLB Operation Register */
96 #define MIDXI (0x28 + MMU_REG_BASE) /* MMU Index Register for
98 #define MIDXD (0x2c + MMU_REG_BASE) /* MMU Index Register for Operand */
100 #define MATM_offset (MATM - MMU_REG_BASE)
101 #define MPSZ_offset (MPSZ - MMU_REG_BASE)
102 #define MASID_offset (MASID - MMU_REG_BASE)
103 #define MESTS_offset (MESTS - MMU_REG_BASE)
104 #define MDEVA_offset (MDEVA - MMU_REG_BASE)
105 #define MDEVP_offset (MDEVP - MMU_REG_BASE)
106 #define MPTB_offset (MPTB - MMU_REG_BASE)
107 #define MSVA_offset (MSVA - MMU_REG_BASE)
108 #define MTOP_offset (MTOP - MMU_REG_BASE)
109 #define MIDXI_offset (MIDXI - MMU_REG_BASE)
110 #define MIDXD_offset (MIDXD - MMU_REG_BASE)