Lines Matching refs:M32R_FPGA_TOP
292 #define M32R_FPGA_TOP (0x000F0000+M32R_SFR_OFFSET) macro
294 #define M32R_FPGA_NUM_OF_CPUS_PORTL (0x00+M32R_FPGA_TOP)
295 #define M32R_FPGA_CPU_NAME0_PORTL (0x10+M32R_FPGA_TOP)
296 #define M32R_FPGA_CPU_NAME1_PORTL (0x14+M32R_FPGA_TOP)
297 #define M32R_FPGA_CPU_NAME2_PORTL (0x18+M32R_FPGA_TOP)
298 #define M32R_FPGA_CPU_NAME3_PORTL (0x1c+M32R_FPGA_TOP)
299 #define M32R_FPGA_MODEL_ID0_PORTL (0x20+M32R_FPGA_TOP)
300 #define M32R_FPGA_MODEL_ID1_PORTL (0x24+M32R_FPGA_TOP)
301 #define M32R_FPGA_MODEL_ID2_PORTL (0x28+M32R_FPGA_TOP)
302 #define M32R_FPGA_MODEL_ID3_PORTL (0x2c+M32R_FPGA_TOP)
303 #define M32R_FPGA_VERSION0_PORTL (0x30+M32R_FPGA_TOP)
304 #define M32R_FPGA_VERSION1_PORTL (0x34+M32R_FPGA_TOP)