Lines Matching refs:cmcv
637 cmcv_reg_t cmcv; in ia64_mca_cmc_vector_setup() local
639 cmcv.cmcv_regval = 0; in ia64_mca_cmc_vector_setup()
640 cmcv.cmcv_mask = 1; /* Mask/disable interrupt at first */ in ia64_mca_cmc_vector_setup()
641 cmcv.cmcv_vector = IA64_CMC_VECTOR; in ia64_mca_cmc_vector_setup()
642 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); in ia64_mca_cmc_vector_setup()
666 cmcv_reg_t cmcv; in ia64_mca_cmc_vector_disable() local
668 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV); in ia64_mca_cmc_vector_disable()
670 cmcv.cmcv_mask = 1; /* Mask/disable interrupt */ in ia64_mca_cmc_vector_disable()
671 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); in ia64_mca_cmc_vector_disable()
674 __func__, smp_processor_id(), cmcv.cmcv_vector); in ia64_mca_cmc_vector_disable()
692 cmcv_reg_t cmcv; in ia64_mca_cmc_vector_enable() local
694 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV); in ia64_mca_cmc_vector_enable()
696 cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */ in ia64_mca_cmc_vector_enable()
697 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); in ia64_mca_cmc_vector_enable()
700 __func__, smp_processor_id(), cmcv.cmcv_vector); in ia64_mca_cmc_vector_enable()