Lines Matching refs:r24
185 ITC_I_AND_D(p10, p11, r18, r24) // insert the instruction TLB entry and
188 MOV_TO_IFA(r22, r24)
191 MOV_TO_ITIR(p8, r25, r24) // change to default page-size for VHPT
199 adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23
201 ITC_D(p7, r24, r25)
383 mov r24=PERCPU_ADDR
396 cmp.ge p10,p11=r16,r24 // access to per_cpu_data?
411 MOV_TO_ITIR(p10, r25, r24)
420 MOV_TO_IPSR(p6, r21, r24)
554 mov r24=PAGE_SHIFT<<2
570 (p7) ptc.l r16,r24
620 mov r24=PAGE_SHIFT<<2
636 (p7) ptc.l r16,r24
675 mov r24=PAGE_SHIFT<<2
690 (p7) ptc.l r16,r24
739 mov.m r24=ar.rnat // M2 (5 cyc)
866 mov ar.rnat=r24 // M2 restore kernel's AR.RNAT
988 (pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat
1552 SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(r15, r24)
1600 SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(r3, r24)
1660 SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(r3, r24)