Lines Matching refs:r22

123 	shr.u r22=r21,3
131 (p8)	shr r22=r22,r27
135 	shr.u r18=r22,PGDIR_SHIFT		// get bottom portion of pgd index bit
150 	shr.u r28=r22,PUD_SHIFT			// shift pud index into position
152 	shr.u r18=r22,PMD_SHIFT			// shift pmd index into position
161 	shr.u r18=r22,PMD_SHIFT			// shift pmd index into position
171 	shr.u r19=r22,PAGE_SHIFT		// shift pte index into position
180 	MOV_FROM_IHA(r22)			// get the VHPT address that caused the TLB miss
188 	MOV_TO_IFA(r22, r24)
236 (p6)	ptc.l r22,r27				// purge PTE page translation
346 	shr.u r22=r16,61			// get the region number into r21
348 	cmp.gt p8,p0=6,r22			// user mode
386 	shr.u r22=r16,61			// get the region number into r21
388 	cmp.gt p8,p0=6,r22			// access to region 0-5
406 	and r22=IA64_ISR_CODE_MASK,r20		// get the isr.code field
413 (p9)	cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22	// check isr.code field
462 	add r22=-PAGE_SHIFT,r18			// adjustment for hugetlb address
465 	shr.u r22=r16,r22
480 	shr.u r18=r22,PUD_SHIFT			// shift pud index into position
482 	shr.u r18=r22,PMD_SHIFT			// shift pmd index into position
492 	shr.u r18=r22,PMD_SHIFT			// shift pmd index into position
499 	shr.u r19=r22,PAGE_SHIFT		// shift pte index into position
770 	addl r22=IA64_RBS_OFFSET,r1		// A    compute base of RBS
774 	lfetch.fault.excl.nt1 [r22]		// M0|1 prefetch RBS
778 	mov.m ar.bspstore=r22			// M2   switch to kernel RBS
831 	sub r22=r19,r18				// A  stime before leave
836 	add r20=r20,r22				// A  sum stime
976 (pUStk) sub r18=r18,r22				// r18=RSE.ndirty*8
1064 	sub r22=r19,r18				// stime before leave kernel
1069 	add r23=r23,r22				// sum stime