Lines Matching refs:r18
113 movl r18=PAGE_SHIFT
127 cmp.ne p8,p0=r18,r26
128 sub r27=r26,r18
130 (p8) dep r25=r18,r25,2,6
135 shr.u r18=r22,PGDIR_SHIFT // get bottom portion of pgd index bit
146 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
147 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
152 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
161 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
165 dep r17=r18,r29,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
167 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pgd,addr)
176 (p7) ld8 r18=[r21] // read *pte
179 (p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
185 ITC_I_AND_D(p10, p11, r18, r24) // insert the instruction TLB entry and
237 (p7) cmp.ne.or.andcm p6,p7=r25,r18 // did *pte change
264 1: ld8 r18=[r17] // read *pte
267 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
270 ITC_I(p0, r18, r19)
282 cmp.ne p7,p0=r18,r19
308 1: ld8 r18=[r17] // read *pte
311 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
314 ITC_D(p0, r18, r19)
326 cmp.ne p7,p0=r18,r19
358 shr.u r18=r16,57 // move address bit 61 to bit 4
360 andcm r18=0x10,r18 // bit 4=~address-bit(61)
364 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
367 ITC_I(p0, r19, r18) // insert the TLB entry
422 ITC_D(p7, r19, r18) // insert the TLB entry
456 MOV_FROM_ITIR(r18)
459 extr.u r18=r18,2,6 // get the faulting page size
462 add r22=-PAGE_SHIFT,r18 // adjustment for hugetlb address
463 add r18=PGDIR_SHIFT-PAGE_SHIFT,r18
466 shr.u r18=r16,r18
476 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
477 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
480 shr.u r18=r22,PUD_SHIFT // shift pud index into position
482 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
488 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=p[u|m]d_offset(pgd,addr)
492 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
495 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
541 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
547 1: ld8 r18=[r17]
549 mov ar.ccv=r18 // set compare value for cmpxchg
550 or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
551 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit
556 (p6) cmp.eq p6,p7=r26,r18 // Only compare if page is present
558 ITC_D(p6, r25, r18) // install updated PTE
566 ld8 r18=[r17] // read PTE again
568 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
575 1: ld8 r18=[r17]
577 or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
580 st8 [r17]=r18 // store back updated PTE
581 ITC_D(p0, r18, r16) // install updated PTE
602 MOV_FROM_IIP(r18)
605 (p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa
608 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
613 1: ld8 r18=[r17]
615 mov ar.ccv=r18 // set compare value for cmpxchg
616 or r25=_PAGE_A,r18 // set the accessed bit
617 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit
622 (p6) cmp.eq p6,p7=r26,r18 // Only if page present
632 ld8 r18=[r17] // read PTE again
634 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
641 1: ld8 r18=[r17]
643 or r18=_PAGE_A,r18 // set the accessed bit
646 st8 [r17]=r18 // store back updated PTE
647 ITC_I(p0, r18, r16) // install updated PTE
662 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
668 1: ld8 r18=[r17]
670 mov ar.ccv=r18 // set compare value for cmpxchg
671 or r25=_PAGE_A,r18 // set the dirty bit
672 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit
677 (p6) cmp.eq p6,p7=r26,r18 // Only if page is present
686 ld8 r18=[r17] // read PTE again
688 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
694 1: ld8 r18=[r17]
696 or r18=_PAGE_A,r18 // set the accessed bit
698 st8 [r17]=r18 // store back updated PTE
699 ITC_D(p0, r18, r16) // install updated PTE
732 mov r18=__IA64_BREAK_SYSCALL // A
750 cmp.eq p0,p7=r18,r17 // I0 is this a system call?
805 MOV_FROM_ITC(p0, p14, r30, r18) // M get cycle for accounting
812 mov r18=ar.bsp // M2 (12 cyc)
826 ld8 r18=[r16],TI_AC_STIME-TI_AC_STAMP // M get last stamp
831 sub r22=r19,r18 // A stime before leave
834 sub r18=r30,r19 // A elapsed time in user
837 add r21=r21,r18 // A sum utime
954 (pKStk) mov r18=r0 // make sure r18 isn't NaT
976 (pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8
990 shl r18=r18,16 // compute ar.rsc to be used for "loadrs"
996 st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs"
1059 ld8 r18=[r16],TI_AC_STIME-TI_AC_STAMP // time at last check in kernel
1064 sub r22=r19,r18 // stime before leave kernel
1067 sub r18=r20,r19 // elapsed time in user mode
1070 add r21=r21,r18 // sum utime
1198 and r18=0xf,r17 // r18 = cr.ipsr.code{3:0}
1201 cmp.ne.or p6,p0=IA64_ISR_CODE_LFETCH,r18
1205 MOV_TO_IPSR(p0, r16, r18)
1230 MOV_FROM_IIM(r18)
1233 shl r18=r18,43 // put sign bit in position (43=64-21)
1237 shr r18=r18,39 // sign extend (39=43-4)
1240 add r17=r17,r18 // now add the offset