Lines Matching refs:mov
41 mov dest=src;; \
46 mov reg=_tmp
49 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
50 mov _idx=0;; \
57 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
58 mov _idx=0;; \
65 mov _reg=rr[_tmp]
88 mov ar.lc=0x08-1;; \
93 mov rr[_idx2]=_tmp;; \
165 mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \
166 mov rr[_tmp1]=_tmp2
210 mov r25=pr;;
236 mov r18=KERNEL_TR_PAGE_SHIFT<<2
239 mov cr.itir=r18
240 mov cr.ifa=r17
241 mov r16=IA64_TR_KERNEL
242 mov r3=ip
263 mov cr.ipsr=r16
266 mov cr.iip=r17
267 mov cr.ifs=r0
282 mov cr.iva=r3
288 mov ar.fpsr=r2
306 (isAP) mov r2=r3
313 mov r16=-1
326 mov r17=rr[r2]
331 mov cr.itir=r17
332 mov cr.ifa=r2
334 mov r19=IA64_TR_CURRENT_STACK
344 mov IA64_KR(CURRENT)=r2 // virtual address
345 mov IA64_KR(CURRENT_STACK)=r16
346 mov r13=r2
357 mov ar.rsc=0 // place RSE in enforced lazy mode
361 mov r18=PERCPU_PAGE_SIZE
377 mov r19=r20
384 (isBP) mov IA64_KR(PER_CPU_DATA)=r19 // per-CPU base for cpu0
385 (isAP) mov IA64_KR(PER_CPU_DATA)=r0 // clear physical per-CPU base
387 mov ar.bspstore=r2 // establish the new RSE stack
389 mov ar.rsc=0x3 // place RSE in eager mode
425 mov r20=ar.lc // preserve ar.lc
426 mov ar.lc=IA64_NUM_DBG_REGS-1
427 mov r18=0
430 1: mov r16=dbr[r18]
435 mov r17=ibr[r18]
442 mov ar.lc=r20 // restore ar.lc
449 mov r20=ar.lc // preserve ar.lc
451 mov ar.lc=IA64_NUM_DBG_REGS-1
452 mov r18=-1
458 mov dbr[r18]=r16
463 mov ibr[r18]=r17
466 mov ar.lc=r20 // restore ar.lc
640 mov loc0=512
641 mov loc1=-1024+16
767 mov f32=f0 // F
772 mov f37=f0 // F
777 mov f40=f0 // F
781 mov f45=f0 // F
785 mov f48=f0 // F
789 mov f53=f0 // F
793 mov f56=f0 // F
797 mov f61=f0 // F
801 mov f64=f0 // F
805 mov f69=f0 // F
809 mov f72=f0 // F
813 mov f77=f0 // F
817 mov f80=f0 // F
821 mov f85=f0 // F
825 mov f88=f0 // F
837 mov f93=f0 // F
841 mov f96=f0 // F
845 mov f101=f0 // F
849 mov f104=f0 // F
853 mov f109=f0 // F
857 mov f112=f0 // F
861 mov f117=f0 // F
865 mov f120=f0 // F
869 mov f125=f0 // F
890 mov r15=ip
898 mov cr.ipsr=r16 // set new PSR
901 mov r19=ar.bsp
902 mov r20=sp
903 mov r14=rp // get return address into a general register
913 mov r18=ar.rnat // save ar.rnat
914 mov ar.bspstore=r17 // this steps on ar.rnat
915 mov cr.iip=r3
916 mov cr.ifs=r0
918 mov ar.rnat=r18 // restore ar.rnat
921 1: mov rp=r14
938 mov r15=ip
946 mov cr.ipsr=r16 // set new PSR
949 mov r14=rp // get return address into a general register
958 mov sp=r20
964 mov r18=ar.rnat // save ar.rnat
965 mov ar.bspstore=r19 // this steps on ar.rnat
966 mov cr.iip=r3
967 mov cr.ifs=r0
969 mov ar.rnat=r18 // restore ar.rnat
972 1: mov rp=r14
980 mov r2=ar.lc
983 mov ar.lc=r32
991 mov ar.lc=r2
1015 mov.m r9=ar.itc // fetch cycle-counter (35 cyc)
1060 mov reg=r32; \
1086 mov b1=r18 // Return location
1089 mov b2=r18 // doing tlb_flush work
1090 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode
1093 mov cr.iip=r17
1095 mov cr.ipsr=r16
1096 mov cr.ifs=r0;;
1134 mov pr=r17,-1;;