Lines Matching refs:ar
49 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
57 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
88 mov ar.lc=0x08-1;; \
116 SAVE_FROM_REG(ar.fpsr,_reg1,_reg2);; \
117 SAVE_FROM_REG(ar.pfs,_reg1,_reg2);; \
118 SAVE_FROM_REG(ar.rnat,_reg1,_reg2);; \
119 SAVE_FROM_REG(ar.unat,_reg1,_reg2);; \
120 SAVE_FROM_REG(ar.bspstore,_reg1,_reg2);; \
134 SAVE_FROM_REG(ar.lc, _reg1, _reg2);; \
288 mov ar.fpsr=r2
357 mov ar.rsc=0 // place RSE in enforced lazy mode
387 mov ar.bspstore=r2 // establish the new RSE stack
389 mov ar.rsc=0x3 // place RSE in eager mode
412 alloc r2=ar.pfs,8,0,2,0
424 alloc r16=ar.pfs,1,0,0,0
425 mov r20=ar.lc // preserve ar.lc
426 mov ar.lc=IA64_NUM_DBG_REGS-1
442 mov ar.lc=r20 // restore ar.lc
447 alloc r16=ar.pfs,1,0,0,0
449 mov r20=ar.lc // preserve ar.lc
451 mov ar.lc=IA64_NUM_DBG_REGS-1
466 mov ar.lc=r20 // restore ar.lc
471 alloc r2=ar.pfs,1,4,0,0
636 alloc r2=ar.pfs,1,2,0,0
901 mov r19=ar.bsp
913 mov r18=ar.rnat // save ar.rnat
914 mov ar.bspstore=r17 // this steps on ar.rnat
918 mov ar.rnat=r18 // restore ar.rnat
964 mov r18=ar.rnat // save ar.rnat
965 mov ar.bspstore=r19 // this steps on ar.rnat
969 mov ar.rnat=r18 // restore ar.rnat
979 .save ar.lc,r2
980 mov r2=ar.lc
983 mov ar.lc=r32
991 mov ar.lc=r2
1015 mov.m r9=ar.itc // fetch cycle-counter (35 cyc)
1033 alloc r16=ar.pfs,1,0,0,0
1059 alloc r16=ar.pfs,1,0,0,0; \
1077 alloc r16=ar.pfs,1,0,0,0;;
1090 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode
1115 RESTORE_REG(ar.fpsr, r25, r17);;
1116 RESTORE_REG(ar.pfs, r25, r17);;
1117 RESTORE_REG(ar.rnat, r25, r17);;
1118 RESTORE_REG(ar.unat, r25, r17);;
1119 RESTORE_REG(ar.bspstore, r25, r17);;
1135 RESTORE_REG(ar.lc, r25, r17);;