Lines Matching refs:r3
249 adds r3=16+64,sp
253 lfetch.fault.excl.nt1 [r3],128
256 lfetch.fault.excl.nt1 [r3],128
259 lfetch.fault.excl [r3]
263 add r3=16,sp
267 lfetch.fault.excl.nt1 [r3],128 // prefetch offset 0x010
269 lfetch.fault.excl.nt1 [r3],128 // prefetch offset 0x090
272 lfetch.fault.excl.nt1 [r3] // prefetch offset 0x110
283 add r3=SW(F3)+16,sp // r3 = &sw->f3
289 stf.spill [r3]=f3,32
298 stf.spill [r3]=f5,32
310 stf.spill [r3]=f13,32
315 stf.spill [r3]=f15,32
320 stf.spill [r3]=f17,32
323 stf.spill [r3]=f19,32
326 stf.spill [r3]=f21,32
329 stf.spill [r3]=f23,32
332 stf.spill [r3]=f25,32
335 stf.spill [r3]=f27,32
338 stf.spill [r3]=f29,32
341 stf.spill [r3]=f31,SW(PR)-SW(F31)
349 st8 [r3]=r21 // save predicate registers
370 adds r3=SW(AR_UNAT)+16,sp
376 ld8 r29=[r3],(SW(B1)-SW(AR_UNAT)) // unat
379 ld8 r22=[r3],16 // restore b1
382 ld8 r24=[r3],16 // restore b3
385 ld8 r26=[r3],16 // restore b5
388 ld8 r17=[r3],(SW(AR_RNAT)-SW(AR_LC)) // ar.lc
391 ld8 r30=[r3] // restore rnat
506 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
525 mov r3=NR_syscalls - 1
531 cmp.leu p6,p7=r15,r3
541 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
547 .mem.offset 8,0; st8.spill [r3]=r10 // clear error indication in slot for r10
555 ld8 r3=[r2] // load pt_regs.r8
558 cmp.ne p6,p0=r3,r0 // is pt_regs.r8!=0?
559 adds r3=16,r2 // r3=&pt_regs.r10
723 adds r3=PT(AR_BSPSTORE)+16,r12 // deferred
727 adds r3=PT(AR_BSPSTORE)+16,r12
739 ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage)
745 ld8 r11=[r3],PT(CR_IIP)-PT(R11)
753 ld8 r28=[r3],16 // M0|1 load cr.iip
758 ld8 r25=[r3],16 // M0|1 load ar.unat
765 ld8 r25=[r3],16 // M0|1 load ar.unat
774 ld8 r27=[r3],PT(PR)-PT(AR_RSC) // M0|1 load ar.rsc
778 ld8 r31=[r3],PT(R1)-PT(PR) // M0|1 load predicates
782 ld8.fill r1=[r3],16 // M0|1 load r1
790 ld8.fill r13=[r3],16 // M0|1
794 ld8.fill r15=[r3] // M0|1 restore r15
867 adds r3=PT(R16)+16,r12
873 ld8.fill r16=[r3],PT(AR_CSD)-PT(R16)
882 ld8 r30=[r3],16 // load ar.csd
886 ld8.fill r8=[r3],16
889 ld8.fill r10=[r3],PT(R17)-PT(R10)
892 ld8.fill r17=[r3],16
895 ld8.fill r19=[r3],16
898 ld8.fill r21=[r3],16
906 ld8.fill r23=[r3],24
910 ld8.fill r26=[r3],16
914 ld8.fill r28=[r3],16
917 ld8.fill r30=[r3],24
920 adds r3=PT(F10)-PT(F6),r3
923 ldf.fill f10=[r3],PT(F8)-PT(F10)
928 ldf.fill f8=[r3],32
934 BSW_0(r2, r3, r15) // switch back to bank 0 (no stop bit required beforehand...)
974 (pUStk) adds r3=TI_AC_LEAVE+IA64_TASK_SIZE,r18
995 (pUStk) st8 [r3]=r22 // save time at leave
999 ld8.fill r3=[r16] // deferred
1004 ld8.fill r3=[r16]
1154 add r3=-8,r3
1157 st8 [r3]=r10
1175 adds r3=PT(R10)+16,r12
1178 ld8 r10=[r3]
1190 ld8 r3=[r2] // load pt_regs.r8
1192 cmp.eq p6,p7=r3,r0 // is pt_regs.r8==0?
1363 add r3 = 0x20, r3
1369 mov b0 = r3
1376 movl r3 = .here;;
1387 mov b6 = r3
1402 movl r3 = ftrace_trace_function;;
1403 ld8 r3 = [r3];;
1404 ld8 r3 = [r3];;
1405 cmp.eq p7,p0 = r2, r3
1418 mov b6 = r3
1432 mov r3 = b0
1436 mov b7 = r3