Lines Matching refs:r2
113 adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp
122 (p6) st8 [r2]=in5 // store TLS in r16 for copy_thread()
144 adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp
153 (p6) st8 [r2]=in4 // store TLS in r13 (tp)
248 adds r2=16+128,sp
255 lfetch.fault.excl.nt1 [r2],128
258 lfetch.fault.excl [r2]
262 add r2=16+3*128,sp
270 lfetch.fault.excl.nt1 [r2],128 // prefetch offset 0x190
273 lfetch.fault.excl.nt1 [r2] // prefetch offset 0x210
279 add r2=SW(F2)+16,sp // r2 = &sw->f2
285 stf.spill [r2]=f2,32
297 stf.spill [r2]=f4,32
309 stf.spill [r2]=f12,32
314 stf.spill [r2]=f14,32
319 stf.spill [r2]=f16,32
322 stf.spill [r2]=f18,32
325 stf.spill [r2]=f20,32
328 stf.spill [r2]=f22,32
331 stf.spill [r2]=f24,32
334 stf.spill [r2]=f26,32
337 stf.spill [r2]=f28,32
340 stf.spill [r2]=f30,SW(AR_UNAT)-SW(F30)
344 st8 [r2]=r29,SW(AR_RNAT)-SW(AR_UNAT) // save ar.unat
348 st8 [r2]=r19,SW(AR_BSPSTORE)-SW(AR_RNAT) // save ar.rnat
351 st8 [r2]=r20 // save ar.bspstore
369 adds r2=SW(AR_BSPSTORE)+16,sp
375 ld8 r27=[r2],(SW(B0)-SW(AR_BSPSTORE)) // bspstore
378 ld8 r21=[r2],16 // restore b0
381 ld8 r23=[r2],16 // restore b2
384 ld8 r25=[r2],16 // restore b4
387 ld8 r16=[r2],(SW(PR)-SW(AR_PFS)) // ar.pfs
390 ld8 r28=[r2] // restore pr
505 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
540 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
546 .mem.offset 0,0; st8.spill [r2]=r8 // store return value in slot for r8
555 ld8 r3=[r2] // load pt_regs.r8
559 adds r3=16,r2 // r3=&pt_regs.r10
621 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
623 ld4 r2=[r2]
626 and r2=_TIF_SYSCALL_TRACEAUDIT,r2
628 cmp.ne p6,p0=r2,r0
636 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
700 RSM_PSR_I(p0, r2, r18) // disable interrupts
710 RSM_PSR_I(pUStk, r2, r18)
717 adds r2=PT(LOADRS)+16,r12
722 ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
726 adds r2=PT(LOADRS)+16,r12
731 ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
736 ld8 r18=[r2],PT(R9)-PT(B6) // load b6
744 ld8 r9=[r2],PT(CR_IPSR)-PT(R9)
752 ld8 r29=[r2],16 // M0|1 load cr.ipsr
757 ld8 r30=[r2],16 // M0|1 load cr.ifs
764 ld8 r30=[r2],16 // M0|1 load cr.ifs
769 ld8 r26=[r2],PT(B0)-PT(AR_PFS) // M0|1 load ar.pfs
773 ld8 r21=[r2],PT(AR_RNAT)-PT(B0) // M0|1 load b0
777 ld8 r24=[r2],PT(AR_FPSR)-PT(AR_RNAT) // M0|1 load ar.rnat (may be garbage)
781 ld8 r20=[r2],PT(R12)-PT(AR_FPSR) // M0|1 load ar.fpsr
793 ld8.fill r12=[r2] // M0|1 restore r12 (sp)
866 adds r2=PT(B6)+16,r12
870 ld8 r28=[r2],8 // load b6
881 ld8 r29=[r2],16 // load b7
885 ld8 r31=[r2],16 // load ar.ssd
888 ld8.fill r9=[r2],16
891 ld8.fill r11=[r2],PT(R18)-PT(R11)
894 ld8.fill r18=[r2],16
897 ld8.fill r20=[r2],16
905 ld8.fill r22=[r2],24
909 ld8.fill r25=[r2],16
913 ld8.fill r27=[r2],16
916 ld8.fill r29=[r2],16
919 ld8.fill r31=[r2],PT(F9)-PT(R31)
922 ldf.fill f9=[r2],PT(F6)-PT(F9)
925 ldf.fill f6=[r2],PT(F7)-PT(F6)
927 ldf.fill f7=[r2],PT(F11)-PT(F7)
933 ldf.fill f11=[r2]
934 BSW_0(r2, r3, r15) // switch back to bank 0 (no stop bit required beforehand...)
986 ld8.fill r2=[r17]
1136 (pLvSys)mov r2=r0
1153 add r2=-8,r2
1156 st8 [r2]=r8
1174 adds r2=PT(R8)+16,r12
1177 ld8 r8=[r2]
1190 ld8 r3=[r2] // load pt_regs.r8
1255 alloc r2=ar.pfs,8,0,1,0
1401 movl r2 = ftrace_stub
1405 cmp.eq p7,p0 = r2, r3
1433 movl r2 = _mcount_ret_helper
1435 mov b6 = r2