Lines Matching refs:d
28 move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0), $r0
29 move.d CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
30 move.d $r1, [$r0]
31 move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1), $r0
32 move.d CONFIG_ETRAX_SDRAM_GRP1_CONFIG, $r1
33 move.d $r1, [$r0]
42 move.d CONFIG_ETRAX_SDRAM_COMMAND, $r2
46 move.d 0x40, $r4 ; Assume 32 bits and CAS latency = 2
47 move.d CONFIG_ETRAX_SDRAM_TIMING, $r1
48 and.d 0x07, $r1 ; Get CAS latency
52 move.d 0x60, $r4
58 move.d CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
59 and.d 0x200, $r1 ; DRAM width is bit 9
66 move.d CONFIG_ETRAX_SDRAM_TIMING, $r1
67 and.d ~(3 << reg_bif_core_rw_sdram_timing___ref___lsb), $r1
68 move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
69 move.d $r1, [$r0]
72 move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd), $r5
74 move.d $r1, [$r5]
77 move.d 10000, $r2
84 1: clear.d $r6
86 or.d $r4, $r6 ; Add calculated mrs
87 move.d $r6, [$r5] ; Write rw_sdram_cmd
89 move.d 4000, $r7
92 cmp.d $r2, $r3 ; Last command?
97 move.d CONFIG_ETRAX_SDRAM_TIMING, $r1
98 move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
99 move.d $r1, [$r0]