Lines Matching refs:timer
64 data = REG_RD(timer, regi_timer0, r_tmr0_data); in get_ns_in_jiffie()
112 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); in reset_watchdog()
127 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); in stop_watchdog()
182 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_clkevt_switch_state()
194 REG_WR(timer, timer_base, rw_tmr0_div, evt); in crisv32_clkevt_next_event()
195 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_clkevt_next_event()
198 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_clkevt_next_event()
213 intr = REG_RD(timer, timer_base, r_masked_intr); in crisv32_timer_interrupt()
217 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_timer_interrupt()
218 REG_WR(timer, timer_base, rw_ack_intr, ack); in crisv32_timer_interrupt()
250 return REG_RD(timer, timer_base, r_time); in crisv32_timer_sched_clock()
261 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_timer_init()
263 timer_intr_mask = REG_RD(timer, timer_base, rw_intr_mask); in crisv32_timer_init()
265 REG_WR(timer, timer_base, rw_intr_mask, timer_intr_mask); in crisv32_timer_init()
337 data = REG_RD(timer, timer_regs[freqs->cpu], in cris_time_freq_notifier()
340 REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div); in cris_time_freq_notifier()