43 			.flags = CLK_PLL,
48 			.flags = CLK_PLL,
53 			.flags = CLK_PLL,
58 			.flags = CLK_PLL,
63 			.flags = CLK_PLL,
68 			.flags = CLK_PLL,
73 			.flags = CLK_PLL,
78 			.flags = CLK_PLL,
83 			.flags = CLK_PLL,
88 			.flags = CLK_PLL,
93 			.flags = CLK_PLL,
98 			.flags = CLK_PLL,
103 			.flags = CLK_PLL,
108 			.flags = CLK_PLL,
113 			.flags = CLK_PLL,
118 			.flags = CLK_PLL,
123 			.flags = CLK_PLL,
175 	pll->flags = PLL_HAS_PRE | PLL_HAS_MUL;  in c6455_setup_clocks()
177 	sysclks[2].flags |= FIXED_DIV_PLL;  in c6455_setup_clocks()
179 	sysclks[3].flags |= FIXED_DIV_PLL;  in c6455_setup_clocks()
213 	pll->flags = PLL_HAS_MUL | PLL_HAS_POST;  in c6457_setup_clocks()
215 	sysclks[1].flags |= FIXED_DIV_PLL;  in c6457_setup_clocks()
217 	sysclks[2].flags |= FIXED_DIV_PLL;  in c6457_setup_clocks()
219 	sysclks[3].flags |= FIXED_DIV_PLL;  in c6457_setup_clocks()
264 	pll->flags = PLL_HAS_MUL;  in c6472_setup_clocks()
267 		sysclks[i].flags |= FIXED_DIV_PLL;  in c6472_setup_clocks()
271 	sysclks[7].flags |= FIXED_DIV_PLL;  in c6472_setup_clocks()
273 	sysclks[8].flags |= FIXED_DIV_PLL;  in c6472_setup_clocks()
275 	sysclks[9].flags |= FIXED_DIV_PLL;  in c6472_setup_clocks()
312 	pll->flags = PLL_HAS_MUL;  in c6474_setup_clocks()
314 	sysclks[7].flags |= FIXED_DIV_PLL;  in c6474_setup_clocks()
316 	sysclks[9].flags |= FIXED_DIV_PLL;  in c6474_setup_clocks()
318 	sysclks[10].flags |= FIXED_DIV_PLL;  in c6474_setup_clocks()
323 	sysclks[12].flags |= FIXED_DIV_PLL;  in c6474_setup_clocks()
361 	pll->flags = PLL_HAS_MUL;  in c6678_setup_clocks()
363 	sysclks[1].flags |= FIXED_DIV_PLL;  in c6678_setup_clocks()
368 	sysclks[3].flags |= FIXED_DIV_PLL;  in c6678_setup_clocks()
371 	sysclks[4].flags |= FIXED_DIV_PLL;  in c6678_setup_clocks()
376 	sysclks[6].flags |= FIXED_DIV_PLL;  in c6678_setup_clocks()
379 	sysclks[7].flags |= FIXED_DIV_PLL;  in c6678_setup_clocks()
384 	sysclks[9].flags |= FIXED_DIV_PLL;  in c6678_setup_clocks()
387 	sysclks[10].flags |= FIXED_DIV_PLL;  in c6678_setup_clocks()
390 	sysclks[11].flags |= FIXED_DIV_PLL;  in c6678_setup_clocks()