Lines Matching refs:BFIN_IRQ
14 #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
15 #define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
16 #define IRQ_GENERIC_ERROR BFIN_IRQ(2) /* GENERIC Error Interrupt */
17 #define IRQ_RTC BFIN_IRQ(3) /* RTC Interrupt */
18 #define IRQ_PPI BFIN_IRQ(4) /* DMA0 Interrupt (PPI) */
19 #define IRQ_SPORT0_RX BFIN_IRQ(5) /* DMA3 Interrupt (SPORT0 RX) */
20 #define IRQ_SPORT0_TX BFIN_IRQ(6) /* DMA4 Interrupt (SPORT0 TX) */
21 #define IRQ_SPORT1_RX BFIN_IRQ(7) /* DMA5 Interrupt (SPORT1 RX) */
22 #define IRQ_SPORT1_TX BFIN_IRQ(8) /* DMA6 Interrupt (SPORT1 TX) */
23 #define IRQ_TWI BFIN_IRQ(9) /* TWI Interrupt */
24 #define IRQ_SPI BFIN_IRQ(10) /* DMA7 Interrupt (SPI) */
25 #define IRQ_UART0_RX BFIN_IRQ(11) /* DMA8 Interrupt (UART0 RX) */
26 #define IRQ_UART0_TX BFIN_IRQ(12) /* DMA9 Interrupt (UART0 TX) */
27 #define IRQ_UART1_RX BFIN_IRQ(13) /* DMA10 Interrupt (UART1 RX) */
28 #define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */
29 #define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */
30 #define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */
31 #define IRQ_PH_INTA_MAC_RX BFIN_IRQ(17) /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */
32 #define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */
33 #define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */
34 #define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */
35 #define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */
36 #define IRQ_TIMER3 BFIN_IRQ(22) /* Timer 3 */
37 #define IRQ_TIMER4 BFIN_IRQ(23) /* Timer 4 */
38 #define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */
39 #define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */
40 #define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */
41 #define IRQ_PF_INTA_PG_INTA BFIN_IRQ(27) /* Ports F&G Interrupt A */
42 #define IRQ_PORTG_INTB BFIN_IRQ(28) /* Port G Interrupt B */
43 #define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */
44 #define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */
45 #define IRQ_PF_INTB_WATCH BFIN_IRQ(31) /* Watchdog & Port F Interrupt B */