Lines Matching refs:C
81 #define C(x) PERF_COUNT_HW_CACHE_##x macro
87 [C(L1D)] = { /* Data bank A */
88 [C(OP_READ)] = {
89 [C(RESULT_ACCESS)] = 0,
90 [C(RESULT_MISS) ] = 0x9A,
92 [C(OP_WRITE)] = {
93 [C(RESULT_ACCESS)] = 0,
94 [C(RESULT_MISS) ] = 0,
96 [C(OP_PREFETCH)] = {
97 [C(RESULT_ACCESS)] = 0,
98 [C(RESULT_MISS) ] = 0,
102 [C(L1I)] = {
103 [C(OP_READ)] = {
104 [C(RESULT_ACCESS)] = 0,
105 [C(RESULT_MISS) ] = 0x83,
107 [C(OP_WRITE)] = {
108 [C(RESULT_ACCESS)] = -1,
109 [C(RESULT_MISS) ] = -1,
111 [C(OP_PREFETCH)] = {
112 [C(RESULT_ACCESS)] = 0,
113 [C(RESULT_MISS) ] = 0,
117 [C(LL)] = {
118 [C(OP_READ)] = {
119 [C(RESULT_ACCESS)] = -1,
120 [C(RESULT_MISS) ] = -1,
122 [C(OP_WRITE)] = {
123 [C(RESULT_ACCESS)] = -1,
124 [C(RESULT_MISS) ] = -1,
126 [C(OP_PREFETCH)] = {
127 [C(RESULT_ACCESS)] = -1,
128 [C(RESULT_MISS) ] = -1,
132 [C(DTLB)] = {
133 [C(OP_READ)] = {
134 [C(RESULT_ACCESS)] = -1,
135 [C(RESULT_MISS) ] = -1,
137 [C(OP_WRITE)] = {
138 [C(RESULT_ACCESS)] = -1,
139 [C(RESULT_MISS) ] = -1,
141 [C(OP_PREFETCH)] = {
142 [C(RESULT_ACCESS)] = -1,
143 [C(RESULT_MISS) ] = -1,
147 [C(ITLB)] = {
148 [C(OP_READ)] = {
149 [C(RESULT_ACCESS)] = -1,
150 [C(RESULT_MISS) ] = -1,
152 [C(OP_WRITE)] = {
153 [C(RESULT_ACCESS)] = -1,
154 [C(RESULT_MISS) ] = -1,
156 [C(OP_PREFETCH)] = {
157 [C(RESULT_ACCESS)] = -1,
158 [C(RESULT_MISS) ] = -1,
162 [C(BPU)] = {
163 [C(OP_READ)] = {
164 [C(RESULT_ACCESS)] = -1,
165 [C(RESULT_MISS) ] = -1,
167 [C(OP_WRITE)] = {
168 [C(RESULT_ACCESS)] = -1,
169 [C(RESULT_MISS) ] = -1,
171 [C(OP_PREFETCH)] = {
172 [C(RESULT_ACCESS)] = -1,
173 [C(RESULT_MISS) ] = -1,