31 	int i_d, i_i;  in generate_cplb_tables_cpu()  local
40 	i_d = i_i = 0;  in generate_cplb_tables_cpu()
46 	i_tbl[i_i].addr = 0;  in generate_cplb_tables_cpu()
47 	i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB;  in generate_cplb_tables_cpu()
65 		i_tbl[i_i].addr = addr;  in generate_cplb_tables_cpu()
66 		i_tbl[i_i++].data = SDRAM_IGENERIC | cplb_pageflags;  in generate_cplb_tables_cpu()
75 	i_tbl[i_i].addr = addr;  in generate_cplb_tables_cpu()
76 	i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_16MB;  in generate_cplb_tables_cpu()
81 	i_tbl[i_i].addr = addr;  in generate_cplb_tables_cpu()
82 	i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;  in generate_cplb_tables_cpu()
92 		i_tbl[i_i].addr = L1_CODE_START;  in generate_cplb_tables_cpu()
93 		i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;  in generate_cplb_tables_cpu()
101 		i_tbl[i_i].addr = COREB_L1_CODE_START;  in generate_cplb_tables_cpu()
102 		i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;  in generate_cplb_tables_cpu()
106 	first_switched_icplb = i_i;  in generate_cplb_tables_cpu()
113 	while (i_i < MAX_CPLBS)  in generate_cplb_tables_cpu()
114 		i_tbl[i_i++].data = 0;  in generate_cplb_tables_cpu()
120 	int i_d, i_i;  in generate_cplb_tables_all()  local
173 	i_i = 0;  in generate_cplb_tables_all()
175 	icplb_bounds[i_i].eaddr = uncached_end;  in generate_cplb_tables_all()
176 	icplb_bounds[i_i++].data = SDRAM_IGENERIC;  in generate_cplb_tables_all()
181 			icplb_bounds[i_i].eaddr = _ramend;  in generate_cplb_tables_all()
182 			icplb_bounds[i_i++].data = 0;  in generate_cplb_tables_all()
185 		icplb_bounds[i_i].eaddr = physical_mem_end;  in generate_cplb_tables_all()
186 		icplb_bounds[i_i++].data = (reserved_mem_icache_on ?  in generate_cplb_tables_all()
190 	icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE;  in generate_cplb_tables_all()
191 	icplb_bounds[i_i++].data = 0;  in generate_cplb_tables_all()
193 	icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;  in generate_cplb_tables_all()
194 	icplb_bounds[i_i++].data = SDRAM_EBIU;  in generate_cplb_tables_all()
196 	icplb_bounds[i_i].eaddr = BOOT_ROM_START;  in generate_cplb_tables_all()
197 	icplb_bounds[i_i++].data = 0;  in generate_cplb_tables_all()
199 	icplb_bounds[i_i].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;  in generate_cplb_tables_all()
200 	icplb_bounds[i_i++].data = SDRAM_IGENERIC;  in generate_cplb_tables_all()
204 		icplb_bounds[i_i].eaddr = L2_START;  in generate_cplb_tables_all()
205 		icplb_bounds[i_i++].data = 0;  in generate_cplb_tables_all()
207 		icplb_bounds[i_i].eaddr = L2_START + L2_LENGTH;  in generate_cplb_tables_all()
208 		icplb_bounds[i_i++].data = L2_IMEMORY;  in generate_cplb_tables_all()
210 	icplb_nr_bounds = i_i;  in generate_cplb_tables_all()