31 	int i_d, i_i;  in generate_cplb_tables_cpu()  local
40 	i_d = i_i = 0;  in generate_cplb_tables_cpu()
44 	d_tbl[i_d].addr = 0;  in generate_cplb_tables_cpu()
45 	d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;  in generate_cplb_tables_cpu()
63 		d_tbl[i_d].addr = addr;  in generate_cplb_tables_cpu()
64 		d_tbl[i_d++].data = SDRAM_DGENERIC | cplb_pageflags;  in generate_cplb_tables_cpu()
73 	d_tbl[i_d].addr = addr;  in generate_cplb_tables_cpu()
74 	d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_16MB;  in generate_cplb_tables_cpu()
79 	d_tbl[i_d].addr = addr;  in generate_cplb_tables_cpu()
80 	d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;  in generate_cplb_tables_cpu()
89 			d_tbl[i_d].addr = L1_DATA_A_START;  in generate_cplb_tables_cpu()
90 			d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;  in generate_cplb_tables_cpu()
98 			d_tbl[i_d].addr = COREB_L1_DATA_A_START;  in generate_cplb_tables_cpu()
99 			d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;  in generate_cplb_tables_cpu()
105 	first_switched_dcplb = i_d;  in generate_cplb_tables_cpu()
111 	while (i_d < MAX_CPLBS)  in generate_cplb_tables_cpu()
112 		d_tbl[i_d++].data = 0;  in generate_cplb_tables_cpu()
120 	int i_d, i_i;  in generate_cplb_tables_all()  local
122 	i_d = 0;  in generate_cplb_tables_all()
135 		dcplb_bounds[i_d].eaddr = uncached_end;  in generate_cplb_tables_all()
137 		dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024 - 1);  in generate_cplb_tables_all()
138 	dcplb_bounds[i_d++].data = SDRAM_DGENERIC;  in generate_cplb_tables_all()
141 		dcplb_bounds[i_d].eaddr = _ramend;  in generate_cplb_tables_all()
142 		dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL;  in generate_cplb_tables_all()
146 		dcplb_bounds[i_d].eaddr = physical_mem_end;  in generate_cplb_tables_all()
147 		dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ?  in generate_cplb_tables_all()
151 	dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE;  in generate_cplb_tables_all()
152 	dcplb_bounds[i_d++].data = 0;  in generate_cplb_tables_all()
154 	dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;  in generate_cplb_tables_all()
155 	dcplb_bounds[i_d++].data = SDRAM_EBIU;  in generate_cplb_tables_all()
157 	dcplb_bounds[i_d].eaddr = BOOT_ROM_START;  in generate_cplb_tables_all()
158 	dcplb_bounds[i_d++].data = 0;  in generate_cplb_tables_all()
160 	dcplb_bounds[i_d].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;  in generate_cplb_tables_all()
161 	dcplb_bounds[i_d++].data = SDRAM_DGENERIC;  in generate_cplb_tables_all()
164 		dcplb_bounds[i_d].eaddr = L2_START;  in generate_cplb_tables_all()
165 		dcplb_bounds[i_d++].data = 0;  in generate_cplb_tables_all()
167 		dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH;  in generate_cplb_tables_all()
168 		dcplb_bounds[i_d++].data = L2_DMEMORY;  in generate_cplb_tables_all()
170 	dcplb_nr_bounds = i_d;  in generate_cplb_tables_all()