Lines Matching refs:CPLB_VALID
12 #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
14 #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
15 #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
23 #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY…
35 #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
47 # define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
49 # define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
98 #define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
99 #define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
100 #define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
102 #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID