Lines Matching refs:x0
75 stp x2, x3, [x0]
76 stp x4, x5, [x0, #16]
77 stp x6, x7, [x0, #32]
78 stp x8, x9, [x0, #48]
79 stp x10, x11, [x0, #64]
80 str x12, [x0, #80]
98 ldp x2, x3, [x0]
99 ldp x4, x5, [x0, #16]
100 ldp x6, x7, [x0, #32]
101 ldp x8, x9, [x0, #48]
102 ldp x10, x11, [x0, #64]
103 ldr x12, [x0, #80]
120 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
121 mov x0, x12
137 bfi x0, x1, #48, #16 // set the ASID
138 msr ttbr0_el1, x0 // set TTBR0
155 mov x0, #3 << 20
156 msr cpacr_el1, x0 // Enable FP/ASIMD
157 mov x0, #1 << 12 // Reset mdscr_el1 and disable
158 msr mdscr_el1, x0 // access to the DCC from EL0
159 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
184 mrs x0, sctlr_el1
185 bic x0, x0, x5 // clear bits
186 orr x0, x0, x6 // set bits