Lines Matching refs:x3
47 add x3, x0, #VCPU_VGIC_CPU
65 str w5, [x3, #VGIC_V2_CPU_VMCR]
66 str w6, [x3, #VGIC_V2_CPU_MISR]
67 CPU_LE( str w7, [x3, #VGIC_V2_CPU_EISR] )
68 CPU_LE( str w8, [x3, #(VGIC_V2_CPU_EISR + 4)] )
69 CPU_LE( str w9, [x3, #VGIC_V2_CPU_ELRSR] )
70 CPU_LE( str w10, [x3, #(VGIC_V2_CPU_ELRSR + 4)] )
71 CPU_BE( str w7, [x3, #(VGIC_V2_CPU_EISR + 4)] )
72 CPU_BE( str w8, [x3, #VGIC_V2_CPU_EISR] )
73 CPU_BE( str w9, [x3, #(VGIC_V2_CPU_ELRSR + 4)] )
74 CPU_BE( str w10, [x3, #VGIC_V2_CPU_ELRSR] )
75 str w11, [x3, #VGIC_V2_CPU_APR]
82 ldr w4, [x3, #VGIC_CPU_NR_LR]
83 add x3, x3, #VGIC_V2_CPU_LR
86 str w5, [x3], #4
107 add x3, x0, #VCPU_VGIC_CPU
110 ldr w4, [x3, #VGIC_V2_CPU_HCR]
111 ldr w5, [x3, #VGIC_V2_CPU_VMCR]
112 ldr w6, [x3, #VGIC_V2_CPU_APR]
123 ldr w4, [x3, #VGIC_CPU_NR_LR]
124 add x3, x3, #VGIC_V2_CPU_LR
125 1: ldr w5, [x3], #4