Lines Matching refs:x3
46 add x3, x2, #CPU_XREG_OFFSET(19)
47 stp x19, x20, [x3]
48 stp x21, x22, [x3, #16]
49 stp x23, x24, [x3, #32]
50 stp x25, x26, [x3, #48]
51 stp x27, x28, [x3, #64]
52 stp x29, lr, [x3, #80]
58 stp x19, x20, [x3, #96]
59 str x21, [x3, #112]
82 add x3, x2, #CPU_XREG_OFFSET(31) // SP_EL0
83 ldp x19, x20, [x3]
84 ldr x21, [x3, #16]
90 add x3, x2, #CPU_XREG_OFFSET(19)
91 ldp x19, x20, [x3]
92 ldp x21, x22, [x3, #16]
93 ldp x23, x24, [x3, #32]
94 ldp x25, x26, [x3, #48]
95 ldp x27, x28, [x3, #64]
96 ldp x29, lr, [x3, #80]
110 add x3, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
111 fpsimd_save x3, 4
117 add x3, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
118 fpsimd_restore x3, 4
129 add x3, x2, #CPU_XREG_OFFSET(4)
130 stp x4, x5, [x3]
131 stp x6, x7, [x3, #16]
132 stp x8, x9, [x3, #32]
133 stp x10, x11, [x3, #48]
134 stp x12, x13, [x3, #64]
135 stp x14, x15, [x3, #80]
136 stp x16, x17, [x3, #96]
137 str x18, [x3, #112]
142 add x3, x2, #CPU_XREG_OFFSET(0)
143 stp x4, x5, [x3]
144 stp x6, x7, [x3, #16]
155 add x3, x2, #CPU_XREG_OFFSET(0)
156 ldp x4, x5, [x3]
157 ldp x6, x7, [x3, #16]
162 ldp x4, x5, [x3, #32]
163 ldp x6, x7, [x3, #48]
164 ldp x8, x9, [x3, #64]
165 ldp x10, x11, [x3, #80]
166 ldp x12, x13, [x3, #96]
167 ldp x14, x15, [x3, #112]
168 ldp x16, x17, [x3, #128]
169 ldr x18, [x3, #144]
175 pop x2, x3
195 add x3, x2, #CPU_SYSREG_OFFSET(MPIDR_EL1)
220 stp x4, x5, [x3]
221 stp x6, x7, [x3, #16]
222 stp x8, x9, [x3, #32]
223 stp x10, x11, [x3, #48]
224 stp x12, x13, [x3, #64]
225 stp x14, x15, [x3, #80]
226 stp x16, x17, [x3, #96]
227 stp x18, x19, [x3, #112]
228 stp x20, x21, [x3, #128]
229 stp x22, x23, [x3, #144]
230 stp x24, x25, [x3, #160]
285 add x3, x2, #CPU_SYSREG_OFFSET(MPIDR_EL1)
287 ldp x4, x5, [x3]
288 ldp x6, x7, [x3, #16]
289 ldp x8, x9, [x3, #32]
290 ldp x10, x11, [x3, #48]
291 ldp x12, x13, [x3, #64]
292 ldp x14, x15, [x3, #80]
293 ldp x16, x17, [x3, #96]
294 ldp x18, x19, [x3, #112]
295 ldp x20, x21, [x3, #128]
296 ldp x22, x23, [x3, #144]
297 ldp x24, x25, [x3, #160]
421 skip_32bit_state x3, 1f
423 add x3, x2, #CPU_SPSR_OFFSET(KVM_SPSR_ABT)
428 stp x4, x5, [x3]
429 stp x6, x7, [x3, #16]
431 add x3, x2, #CPU_SYSREG_OFFSET(DACR32_EL2)
434 stp x4, x5, [x3]
438 str x6, [x3, #16]
442 str x7, [x3, #24]
447 skip_32bit_state x3, 1f
449 add x3, x2, #CPU_SPSR_OFFSET(KVM_SPSR_ABT)
450 ldp x4, x5, [x3]
451 ldp x6, x7, [x3, #16]
457 add x3, x2, #CPU_SYSREG_OFFSET(DACR32_EL2)
458 ldp x4, x5, [x3]
463 ldr x7, [x3, #24]
479 mov x3, #(1 << 30)
480 msr fpexc32_el2, x3
556 mrs x3, cntv_ctl_el0
557 and x3, x3, #3
562 mrs x3, cntv_cval_el0
563 str x3, [x0, #VCPU_TIMER_CNTV_CVAL]
592 ldr x3, [x2, #KVM_TIMER_CNTVOFF]
593 msr cntvoff_el2, x3
626 add x4, x3, #DEBUG_BCR
628 add x4, x3, #DEBUG_BVR
632 add x4, x3, #DEBUG_WCR
634 add x4, x3, #DEBUG_WVR
655 add x4, x3, #DEBUG_BCR
657 add x4, x3, #DEBUG_BVR
661 add x4, x3, #DEBUG_WCR
663 add x4, x3, #DEBUG_WVR
672 skip_fpsimd_state x3, 1f
677 skip_fpsimd_state x3, 1f
698 skip_32bit_state x3, 1f
703 pop x2, x3
731 add x3, x0, #VCPU_HOST_DEBUG_STATE
748 skip_debug_state x3, 1f
749 ldr x3, [x0, #VCPU_DEBUG_PTR]
750 kern_hyp_va x3
769 skip_debug_state x3, 1f
770 ldr x3, [x0, #VCPU_DEBUG_PTR]
771 kern_hyp_va x3
791 skip_debug_state x3, 1f
796 add x3, x0, #VCPU_HOST_DEBUG_STATE
897 ldp x2, x3, [x1]
899 add x0, x0, x3
902 mrs x3, esr_el2
971 push x2, x3
979 mrs x3, vttbr_el2 // If vttbr is valid, the 64bit guest
980 cbnz x3, el1_trap // called HVC
983 pop x2, x3
1000 mov x2, x3
1039 mrs x3, par_el1
1040 push x3, xzr
1054 mrs x3, par_el1
1057 tbnz x3, #0, 3f // Bail out if we failed the translation
1058 ubfx x3, x3, #12, #36 // Extract IPA
1059 lsl x3, x3, #4 // and present it like HPFAR
1062 1: mrs x3, hpfar_el2
1068 str x3, [x0, #VCPU_HPFAR_EL2]
1078 3: pop x2, x3
1085 push x2, x3