279 	int shift;  in aarch64_get_imm_shift_mask()  local
284 		shift = 0;  in aarch64_get_imm_shift_mask()
288 		shift = 5;  in aarch64_get_imm_shift_mask()
292 		shift = 5;  in aarch64_get_imm_shift_mask()
296 		shift = 5;  in aarch64_get_imm_shift_mask()
300 		shift = 10;  in aarch64_get_imm_shift_mask()
304 		shift = 12;  in aarch64_get_imm_shift_mask()
308 		shift = 15;  in aarch64_get_imm_shift_mask()
313 		shift = 10;  in aarch64_get_imm_shift_mask()
317 		shift = 16;  in aarch64_get_imm_shift_mask()
324 	*shiftp = shift;  in aarch64_get_imm_shift_mask()
339 	int shift;  in aarch64_insn_decode_immediate()  local
343 		shift = 0;  in aarch64_insn_decode_immediate()
350 		if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {  in aarch64_insn_decode_immediate()
357 	return (insn >> shift) & mask;  in aarch64_insn_decode_immediate()
364 	int shift;  in aarch64_insn_encode_immediate()  local
368 		shift = 0;  in aarch64_insn_encode_immediate()
377 		if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {  in aarch64_insn_encode_immediate()
385 	insn &= ~(mask << shift);  in aarch64_insn_encode_immediate()
386 	insn |= (imm & mask) << shift;  in aarch64_insn_encode_immediate()
395 	int shift;  in aarch64_insn_encode_register()  local
405 		shift = 0;  in aarch64_insn_encode_register()
408 		shift = 5;  in aarch64_insn_encode_register()
412 		shift = 10;  in aarch64_insn_encode_register()
415 		shift = 16;  in aarch64_insn_encode_register()
423 	insn &= ~(GENMASK(4, 0) << shift);  in aarch64_insn_encode_register()
424 	insn |= reg << shift;  in aarch64_insn_encode_register()
632 	int shift;  in aarch64_insn_gen_load_store_pair()  local
657 		shift = 2;  in aarch64_insn_gen_load_store_pair()
663 		shift = 3;  in aarch64_insn_gen_load_store_pair()
681 					     offset >> shift);  in aarch64_insn_gen_load_store_pair()
779 			      int imm, int shift,  in aarch64_insn_gen_movewide()  argument
804 		BUG_ON(shift != 0 && shift != 16);  in aarch64_insn_gen_movewide()
808 		BUG_ON(shift != 0 && shift != 16 && shift != 32 &&  in aarch64_insn_gen_movewide()
809 		       shift != 48);  in aarch64_insn_gen_movewide()
816 	insn |= (shift >> 4) << 21;  in aarch64_insn_gen_movewide()
826 					 int shift,  in aarch64_insn_gen_add_sub_shifted_reg()  argument
852 		BUG_ON(shift & ~(SZ_32 - 1));  in aarch64_insn_gen_add_sub_shifted_reg()
856 		BUG_ON(shift & ~(SZ_64 - 1));  in aarch64_insn_gen_add_sub_shifted_reg()
870 	return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);  in aarch64_insn_gen_add_sub_shifted_reg()
1008 					 int shift,  in aarch64_insn_gen_logical_shifted_reg()  argument
1046 		BUG_ON(shift & ~(SZ_32 - 1));  in aarch64_insn_gen_logical_shifted_reg()
1050 		BUG_ON(shift & ~(SZ_64 - 1));  in aarch64_insn_gen_logical_shifted_reg()
1064 	return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);  in aarch64_insn_gen_logical_shifted_reg()