235 	int i, max_slots, ctrl_reg, val_reg, reg_enable;  in hw_breakpoint_control()  local
241 		ctrl_reg = AARCH64_DBG_REG_BCR;  in hw_breakpoint_control()
248 		ctrl_reg = AARCH64_DBG_REG_WCR;  in hw_breakpoint_control()
274 		write_wb_reg(ctrl_reg, i,  in hw_breakpoint_control()
279 		write_wb_reg(ctrl_reg, i, 0);  in hw_breakpoint_control()
586 	u32 ctrl_reg;  in breakpoint_handler()  local
610 		ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i);  in breakpoint_handler()
611 		decode_ctrl_reg(ctrl_reg, &ctrl);  in breakpoint_handler()
662 	u32 ctrl_reg;  in watchpoint_handler()  local
697 		ctrl_reg = read_wb_reg(AARCH64_DBG_REG_WCR, i);  in watchpoint_handler()
698 		decode_ctrl_reg(ctrl_reg, &ctrl);  in watchpoint_handler()