Lines Matching refs:clock

14 #include <dt-bindings/clock/mt8173-clk.h>
106 		compatible = "fixed-clock";
107 		#clock-cells = <0>;
108 		clock-frequency = <26000000>;
109 		clock-output-names = "clk26m";
113 		compatible = "fixed-clock";
114 		#clock-cells = <0>;
115 		clock-frequency = <32000>;
116 		clock-output-names = "clk32k";
120 		compatible = "fixed-clock";
121 		#clock-cells = <0>;
122 		clock-frequency = <0>;
123 		clock-output-names = "cpum_ck";
145 		topckgen: clock-controller@10000000 {
148 			#clock-cells = <1>;
154 			#clock-cells = <1>;
161 			#clock-cells = <1>;
240 			clock-names = "mfg", "mm", "venc", "venc_lt";
258 			clock-names = "spi", "wrap";
270 		apmixedsys: clock-controller@10209000 {
273 			#clock-cells = <1>;
295 			clock-names = "baud", "bus";
305 			clock-names = "baud", "bus";
315 			clock-names = "baud", "bus";
325 			clock-names = "baud", "bus";
334 			clock-div = <16>;
337 			clock-names = "main", "dma";
350 			clock-div = <16>;
353 			clock-names = "main", "dma";
366 			clock-div = <16>;
369 			clock-names = "main", "dma";
386 			clock-names = "parent-clk", "sel-clk", "spi-clk";
395 			clock-div = <16>;
398 			clock-names = "main", "dma";
411 			clock-div = <16>;
414 			clock-names = "main", "dma";
427 			clock-div = <16>;
430 			clock-names = "main", "dma";
453 			clock-names = "infra_sys_audio_clk",
465 			assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
476 			clock-names = "source", "hclk";
487 			clock-names = "source", "hclk";
498 			clock-names = "source", "hclk";
509 			clock-names = "source", "hclk";
513 		mmsys: clock-controller@14000000 {
516 			#clock-cells = <1>;
519 		imgsys: clock-controller@15000000 {
522 			#clock-cells = <1>;
525 		vdecsys: clock-controller@16000000 {
528 			#clock-cells = <1>;
531 		vencsys: clock-controller@18000000 {
534 			#clock-cells = <1>;
537 		vencltsys: clock-controller@19000000 {
540 			#clock-cells = <1>;