Lines Matching refs:clock
101 clock-names = "refclk", "timclk", "apb_pclk";
102 #clock-cells = <1>;
103 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
105 …assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz…
127 clock-names = "apb_pclk";
139 clock-names = "mclk", "apb_pclk";
147 clock-names = "KMIREFCLK", "apb_pclk";
155 clock-names = "KMIREFCLK", "apb_pclk";
163 clock-names = "uartclk", "apb_pclk";
171 clock-names = "uartclk", "apb_pclk";
179 clock-names = "uartclk", "apb_pclk";
187 clock-names = "uartclk", "apb_pclk";
195 clock-names = "wdogclk", "apb_pclk";
203 clock-names = "timclken1", "timclken2", "apb_pclk";
211 clock-names = "timclken1", "timclken2", "apb_pclk";
238 clock-names = "apb_pclk";
254 clock-names = "clcdclk", "apb_pclk";
275 clock-frequency = <25175000>;
298 compatible = "fixed-clock";
299 #clock-cells = <0>;
300 clock-frequency = <24000000>;
301 clock-output-names = "v2m:clk24mhz";
305 compatible = "fixed-clock";
306 #clock-cells = <0>;
307 clock-frequency = <1000000>;
308 clock-output-names = "v2m:refclk1mhz";
312 compatible = "fixed-clock";
313 #clock-cells = <0>;
314 clock-frequency = <32768>;
315 clock-output-names = "v2m:refclk32khz";
375 /* MCC static memory clock */
379 #clock-cells = <0>;
380 clock-output-names = "v2m:oscclk0";
384 /* CLCD clock */
388 #clock-cells = <0>;
389 clock-output-names = "v2m:oscclk1";
393 /* IO FPGA peripheral clock */
397 #clock-cells = <0>;
398 clock-output-names = "v2m:oscclk2";