Lines Matching refs:an

220 	  This option adds an alternative code sequence to work around ARM
221 	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
222 	  AXI master interface and an L2 cache.
224 	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
233 	  the kernel if an affected CPU is detected.
241 	  This option adds an alternative code sequence to work around ARM
242 	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
243 	  master interface and an L2 cache.
254 	  the kernel if an affected CPU is detected.
262 	  This option adds an alternative code sequence to work around ARM
276 	  only patch the kernel if an affected CPU is detected.
284 	  This option adds an alternative code sequence to work around ARM
285 	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
297 	  the kernel if an affected CPU is detected.
305 	  This option adds an alternative code sequence to work around ARM
315 	  the kernel if an affected CPU is detected.
324 	  This option adds an alternative code sequence to work around ARM
336 	  the kernel if an affected CPU is detected.
345 	  This option adds an alternative code sequence to work around ARM
348 	  When running a compat (AArch32) userspace on an affected Cortex-A53
357 	  the kernel if an affected CPU is detected.
362 	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
368 	  a subsequent memory access to use an incorrect address on Cortex-A53
621 	  on an external transaction monitoring block called a global
670 	  set this bit instead of raising an access flag fault.
744 	  allow the kernel to be booted as an EFI application. This