Lines Matching refs:r1
118 mrc p15, 0, r1, c1, c0, 1
119 bic r1, r1, #1
120 mcr p15, 0, r1, c1, c0, 1
147 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
148 msr cpsr_c, r1 @ reset CPSR
149 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
150 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
151 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
152 bic r1, r1, #0x0086 @ ........B....CA.
153 bic r1, r1, #0x3900 @ ..VIZ..S........
156 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
157 bic r1, r1, #0x0001 @ ...............M
159 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
215 clean_d_cache r0, r1
234 sub r3, r1, r0 @ calculate total size
243 cmp r0, r1
267 cmp r0, r1
289 cmp r0, r1
306 add r1, r0, r1
310 cmp r0, r1
332 tst r1, #CACHELINESIZE - 1
333 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
336 cmp r0, r1
353 cmp r0, r1
371 cmp r0, r1
383 add r1, r1, r0
397 add r1, r1, r0
459 subs r1, r1, #CACHELINESIZE
474 clean_d_cache r1, r2
513 and ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_RDONLY) & ~(4 << 2)
516 moveq r1, #L_PTE_MT_WRITETHROUGH
517 and r1, r1, #L_PTE_MT_MASK
519 ldr ip, [ip, r1]
554 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr