Lines Matching refs:r0
127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
128 bic r0, r0, #0x1800 @ ...IZ...........
129 bic r0, r0, #0x0006 @ .............CA.
130 mcr p15, 0, r0, c1, c0, 0 @ disable caches
163 ret r0
180 mov r0, #1
181 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
192 mov r0, #0
193 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
215 clean_d_cache r0, r1
234 sub r3, r1, r0 @ calculate total size
239 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
240 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
241 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
242 add r0, r0, #CACHELINESIZE
243 cmp r0, r1
264 bic r0, r0, #CACHELINESIZE - 1
265 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
266 add r0, r0, #CACHELINESIZE
267 cmp r0, r1
269 mov r0, #0
270 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
271 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
285 bic r0, r0, #CACHELINESIZE - 1
286 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
287 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
288 add r0, r0, #CACHELINESIZE
289 cmp r0, r1
291 mov r0, #0
292 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
293 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
306 add r1, r0, r1
307 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
308 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
309 add r0, r0, #CACHELINESIZE
310 cmp r0, r1
312 mov r0, #0
313 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
314 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
329 tst r0, #CACHELINESIZE - 1
330 bic r0, r0, #CACHELINESIZE - 1
331 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
334 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
335 add r0, r0, #CACHELINESIZE
336 cmp r0, r1
338 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
350 bic r0, r0, #CACHELINESIZE - 1
351 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
352 add r0, r0, #CACHELINESIZE
353 cmp r0, r1
355 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
367 bic r0, r0, #CACHELINESIZE - 1
368 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
369 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
370 add r0, r0, #CACHELINESIZE
371 cmp r0, r1
373 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
383 add r1, r1, r0
397 add r1, r1, r0
457 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
458 add r0, r0, #CACHELINESIZE
477 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
541 stmia r0, {r4 - r9} @ store cp regs
546 ldmia r0, {r4 - r9} @ load cp regs
556 mov r0, r9 @ control register
566 mov r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
567 orr r0, r0, #1 << 13 @ Its undefined whether this
568 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
572 mrc p15, 0, r0, c1, c0, 0 @ get control register
573 bic r0, r0, r5
574 orr r0, r0, r6