Lines Matching refs:r0
92 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
93 bic r0, r0, #0x1800 @ ...IZ...........
94 bic r0, r0, #0x0006 @ .............CA.
95 mcr p15, 0, r0, c1, c0, 0 @ disable caches
122 ret r0
139 mov r0, #1
140 mcr p14, 0, r0, c7, c0, 0 @ go to idle
151 mov r0, #0
152 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
174 clean_d_cache r0, r1
194 sub r3, r1, r0 @ calculate total size
199 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
200 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
201 add r0, r0, #CACHELINESIZE
202 cmp r0, r1
226 bic r0, r0, #CACHELINESIZE - 1
227 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
228 add r0, r0, #CACHELINESIZE
229 cmp r0, r1
231 mov r0, #0
232 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
233 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
234 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
247 add r1, r0, r1
248 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
249 add r0, r0, #CACHELINESIZE
250 cmp r0, r1
252 mov r0, #0
253 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
254 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
255 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
270 tst r0, #CACHELINESIZE - 1
271 bic r0, r0, #CACHELINESIZE - 1
272 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
275 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
276 add r0, r0, #CACHELINESIZE
277 cmp r0, r1
279 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
291 bic r0, r0, #CACHELINESIZE - 1
292 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
293 add r0, r0, #CACHELINESIZE
294 cmp r0, r1
296 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
308 bic r0, r0, #CACHELINESIZE - 1
309 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
310 add r0, r0, #CACHELINESIZE
311 cmp r0, r1
313 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
323 add r1, r1, r0
347 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
348 add r0, r0, #CACHELINESIZE
368 orr r0, r0, #0x18 @ cache the page table in L2
369 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
426 stmia r0, {r4 - r9} @ store cp regs
431 ldmia r0, {r4 - r9} @ load cp regs
444 mov r0, r9 @ control register
451 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
452 msr cpsr_c, r0
460 mov r0, #1 << 6 @ cp6 access for early sched_clock
461 mcr p15, 0, r0, c15, c1, 0 @ write CP access register
463 mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
464 and r0, r0, #2 @ preserve bit P bit setting
465 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
466 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
472 mrc p15, 1, r0, c0, c0, 1 @ get L2 present information
473 ands r0, r0, #0xf8
477 mrc p15, 0, r0, c1, c0, 0 @ get control register
478 bic r0, r0, r5 @ ..V. ..R. .... ..A.
479 orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu)