Lines Matching refs:r10
113 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
147 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
194 mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
195 teq r4, r10 @ Already restored?
197 mrc p15, 0, r10, c15, c0, 0 @ Read Power register
198 teq r5, r10 @ Already restored?
223 stmfd sp!, {r6 - r10}
228 mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
229 stmia r0!, {r6 - r10}
230 ldmfd sp!, {r6 - r10}
235 ldmia r0!, {r6 - r10}
240 mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC
269 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
276 mov r10, #0
286 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
433 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
434 teq r0, r10
438 ldr r10, =0x00000c09 @ Cortex-A9 primary part number
439 teq r0, r10
443 ldr r10, =0x00000c0f @ Cortex-A15 primary part number
444 teq r0, r10
448 mov r10, #0
449 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
451 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
452 v7_ttb_setup r10, r4, r5, r8, r3 @ TTBCR, TTBRx setup