Lines Matching refs:r0
33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
34 bic r0, r0, #0x1000 @ ...i............
35 bic r0, r0, #0x0006 @ .............ca.
36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
60 bx r0
82 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
83 add r0, r0, r2
101 stmia r0!, {r4 - r5}
114 stmia r0, {r5 - r11}
122 ldmia r0!, {r4 - r5}
125 ldmia r0, {r5 - r11}
150 mov r0, r8 @ control register
187 stmia r0!, {r4 - r5}
193 ldmia r0!, {r4 - r5}
229 stmia r0!, {r6 - r10}
235 ldmia r0!, {r6 - r10}
278 stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6
280 ldmia r12, {r0-r5, lr}
282 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
283 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
284 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
285 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
286 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
287 mcreq p15, 0, r0, c1, c0, 1
302 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
303 orreq r0, r0, #(1 << 6) @ set IBE to 1
304 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
308 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
309 orreq r0, r0, #(1 << 5) @ set L1NEON to 1
310 orreq r0, r0, #(1 << 9) @ set PLDNOP to 1
311 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
315 mrceq p15, 1, r0, c9, c0, 2 @ read L2 cache aux ctrl register
316 tsteq r0, #1 << 22
317 orreq r0, r0, #(1 << 22) @ set the Write Allocate disable bit
318 mcreq p15, 1, r0, c9, c0, 2 @ write the L2 cache aux ctrl register
325 mrcle p15, 0, r0, c15, c0, 1 @ read diagnostic register
326 orrle r0, r0, #1 << 4 @ set bit #4
327 mcrle p15, 0, r0, c15, c0, 1 @ write diagnostic register
333 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
334 orreq r0, r0, #1 << 12 @ set bit #12
335 orreq r0, r0, #1 << 22 @ set bit #22
336 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
340 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
341 orreq r0, r0, #1 << 6 @ set bit #6
342 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
347 mrclt p15, 0, r0, c15, c0, 1 @ read diagnostic register
348 orrlt r0, r0, #1 << 11 @ set bit #11
349 mcrlt p15, 0, r0, c15, c0, 1 @ write diagnostic register
357 mrcle p15, 0, r0, c1, c0, 1 @ read aux control register
358 orrle r0, r0, #1 << 1 @ disable loop buffer
359 mcrle p15, 0, r0, c1, c0, 1 @ write aux control register
389 mrc p15, 1, r0, c15, c1, 1
390 orr r0, r0, #PJ4B_CLEAN_LINE
391 orr r0, r0, #PJ4B_INTER_PARITY
392 bic r0, r0, #PJ4B_STATIC_BP
393 mcr p15, 1, r0, c15, c1, 1
396 mrc p15, 1, r0, c15, c1, 2
397 bic r0, r0, #PJ4B_FAST_LDR
398 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
399 mcr p15, 1, r0, c15, c1, 2
402 mrc p15, 1, r0, c15, c2, 0
404 orr r0, r0, #PJ4B_SMP_CFB
406 orr r0, r0, #PJ4B_L1_PAR_CHK
407 orr r0, r0, #PJ4B_BROADCAST_CACHE
408 mcr p15, 1, r0, c15, c2, 0
411 mrc p15, 1, r0, c15, c1, 0
412 orr r0, r0, #PJ4B_WFI_WFE
413 mcr p15, 1, r0, c15, c1, 0
419 stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6
421 ldmia r12, {r0-r5, lr}
424 and r0, r9, #0xff000000 @ ARM?
425 teq r0, #0x41000000
430 ubfx r0, r9, #4, #12 @ primary part number
434 teq r0, r10
439 teq r0, r10
444 teq r0, r10
460 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
461 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
462 teq r0, #(1 << 12) @ check if ThumbEE is present
466 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
467 orr r0, r0, #1 @ set the 1st bit in order to
468 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
478 mrc p15, 0, r0, c1, c0, 0 @ read control register
479 bic r0, r0, r3 @ clear bits them
480 orr r0, r0, r6 @ set them
481 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions