Lines Matching refs:c0
42 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
60 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
62 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
79 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
107 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
109 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
114 mcr p15, 0, r1, c13, c0, 1 @ set context ID
142 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
144 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
145 mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1
147 mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
148 mrc p15, 0, r8, c1, c0, 2 @ co-processor access control
149 mrc p15, 0, r9, c1, c0, 0 @ control register
160 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
162 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
164 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
167 mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0
168 mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1
169 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
171 mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register
172 mcr p15, 0, r8, c1, c0, 2 @ co-processor access control
200 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
203 ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
213 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
218 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
225 mrc p15, 0, r0, c1, c0, 0 @ read control register
237 mrc p15, 0, r5, c0, c0, 0 @ get processor id
239 mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
241 mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg