Lines Matching refs:r0
43 mov r0, #0
44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
57 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
58 bic r0, r0, #0x1000 @ ...i............
59 bic r0, r0, #0x000e @ ............wca.
60 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 ret r0
102 mov r0, r0 @ 4 nop padding
103 mov r0, r0
104 mov r0, r0
105 mov r0, r0 @ 4 nop padding
106 mov r0, r0
107 mov r0, r0
108 mov r0, #0
111 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
113 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
114 mov r0, r0 @ safety
115 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
130 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
131 add r0, r0, #DCACHELINESIZE
151 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
167 mov r0, r0
168 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
169 mcr p15, 0, r0, c7, c10, 4 @ drain WB
181 stmia r0, {r4 - r6} @ store cp regs
186 ldmia r0, {r4 - r6} @ load cp regs
196 mov r0, r6 @ control register
203 mov r0, #0
204 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
205 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
207 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
211 mrc p15, 0, r0, c1, c0 @ get control register v4
212 bic r0, r0, r5
213 orr r0, r0, r6